How to work with the Libero IDE on existing projects (by Martin, 17. May 2013)

The version of the Libero IDE this tutorial is based upon is 9.1.5.1 SP5.
In order to better handle constraints files, the Synplify Pro software has been
updated to version G-2012.09A-SP1, which can be obtained somwhere on 
Actels webpage.

1)   Open the *.prj-file with Libero IDE. Several error messages will appear due to 
     missing files (which you will create automatically in the following steps). Do not bother.

2A)  Click on "Synthesis" in the project flow tab.

2B)  Import synthesis constraint file by Implementation Options -> Constraints -> <click to add file...>
     and open "syn_const.sdc" (or any other constraints file). Unfortunately, Synplify Pro forgets
     about this step after closure, so you have to repeat this every time you re-open Synplify
     
     (IMPORTANT! Disable FSM Compiler)
    
2C)  Hit F8 or Run->Run. Let the tool finish.

3A)  Open Designer by clicking on "Place & Route" in the project flow tab. 
     Add the physical design constraints file and confirm. Choose the appropriate values from
     the following dialouge boxes: 
     RTAX2000S, 256 CQFP, Speed STD -> IO-Standards as desired -> Operating Conditions as desired
     
3B)  Import the pinout file if desired by File -> Import Source Files... -> Add -> ...
     Confirm the following dialouges with default values

3C)  Click on "Compile" and choose default options in the following dialouges (or adjust if
     necessary). Wait for tool to finish.
     Check, if your clock-signals are connected to the hardwired clock network by scrolling 
     a little up through the produced log in the bottom og the screen. There should be 
     something like this:

     Post-Combiner device utilization:
         SEQUENTIAL (R-cells)         Used: 6671  Total: 10752   (62.04%)
         COMB (C-cells)               Used: 10618  Total: 21504   (49.38%)
         LOGIC (R+C cells)            Used: 17289  Total: 32256   (53.60%)
         RAM/FIFO                     Used:   23  Total:   64
         IO w/Clocks                  Used:   56  Total:  136
         CLOCK (Routed)               Used:    0  Total:    4
         HCLOCK (Hardwired)           Used:    1  Total:    4
         PLL                          Used:    0  Total:    0
    
     Do the same for your other global signals, which should be either mapped to hardwired 
     (HCLOCK) or routed (CLOCK) nets.

3D)  Click on "Layout". Leave settings in the following dialouge at their defaults or
     adjust as you see fit. Let the tool finish.

3E)  Click on "Generate Programming File..." and do the necessary adjustments in
     the following dialouge box.

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!! IMPORTANT: For flight hardware, the option "Use the JTAG pull-up resistor" !!!
!!!            has to be DISABLED. Otherwise we might lose the entire Chip to  !!!
!!!            an SEU (you do not want that, do you??)                         !!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

     Let the tool finish.