quartus/irenacore.asm.rpt:Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
quartus/irenacore.fit.rpt:  5. I/O Assignment Warnings
quartus/irenacore.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
quartus/irenacore.fit.rpt:; I/O Assignment Warnings                             ;
quartus/irenacore.fit.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/irenacore.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
quartus/irenacore.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
quartus/irenacore.fit.rpt:Warning (176674): Following 6 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
quartus/irenacore.fit.rpt:    Warning (176118): Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)"
quartus/irenacore.fit.rpt:    Warning (176118): Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)"
quartus/irenacore.fit.rpt:    Warning (176118): Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)"
quartus/irenacore.fit.rpt:    Warning (176118): Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
quartus/irenacore.fit.rpt:    Warning (176118): Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
quartus/irenacore.fit.rpt:    Warning (176118): Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
quartus/irenacore.fit.rpt:Warning (176225): Can't pack node irenacore:irena|a_data[9] to I/O pin
quartus/irenacore.fit.rpt:    Warning (176228): Can't pack node irenacore:irena|a_data[9] and I/O node adc_sdata[9] -- I/O node is a dedicated I/O pin
quartus/irenacore.fit.rpt:Warning (176225): Can't pack node irenacore:irena|a_data[10] to I/O pin
quartus/irenacore.fit.rpt:    Warning (176228): Can't pack node irenacore:irena|a_data[10] and I/O node adc_sdata[10] -- I/O node is a dedicated I/O pin
quartus/irenacore.fit.rpt:Warning (176225): Can't pack node irenacore:irena|a_data[8] to I/O pin
quartus/irenacore.fit.rpt:    Warning (176228): Can't pack node irenacore:irena|a_data[8] and I/O node adc_sdata[8] -- I/O node is a dedicated I/O pin
quartus/irenacore.fit.rpt:Warning (169180): Following 18 pins must use external clamping diodes.
quartus/irenacore.fit.rpt:Info: Quartus II 32-bit Fitter was successful. 0 errors, 17 warnings
quartus/irenacore.map.rpt:; conf3         ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/irenacore.map.rpt:; fifo_empty    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/irenacore.map.rpt:; rro  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/irenacore.map.rpt:; rbusy ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/irenacore.map.rpt:; empty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/irenacore.map.rpt:; rro  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/irenacore.map.rpt:; a          ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/irenacore.map.rpt:; b          ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/irenacore.map.rpt:; apeak      ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/irenacore.map.rpt:; bzero      ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/irenacore.map.rpt:; c1   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/irenacore.map.rpt:; c2   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/irenacore.map.rpt:; c3   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/irenacore.map.rpt:; c4   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/irenacore.map.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/irenacore.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at adc128/sfilter.v(443)
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at ms5540c.v(130): Parameter Declaration in module "ms5540c" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at adccntl.v(140): Parameter Declaration in module "adc_channels" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(41): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(42): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(43): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(44): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(45): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(46): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(47): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(55): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(56): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(57): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(58): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(86): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(87): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(88): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(89): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(91): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(92): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at sfilter.v(899): Parameter Declaration in module "trigger" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at irena_core.v(82): truncated value with size 32 to match size of target (16)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at irena_core.v(199): truncated value with size 32 to match size of target (18)
quartus/irenacore.map.rpt:Warning (10036): Verilog HDL or VHDL warning at adccntl.v(116): object "phmm" assigned a value but never read
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at adccntl.v(118): truncated value with size 32 to match size of target (20)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(910): truncated value with size 32 to match size of target (7)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(948): truncated value with size 32 to match size of target (6)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(968): truncated value with size 32 to match size of target (10)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1715): truncated value with size 32 to match size of target (7)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1720): truncated value with size 32 to match size of target (7)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1737): truncated value with size 30 to match size of target (16)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1078): truncated value with size 32 to match size of target (3)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1105): truncated value with size 32 to match size of target (5)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1107): truncated value with size 32 to match size of target (5)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1136): truncated value with size 32 to match size of target (16)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1189): truncated value with size 32 to match size of target (18)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1205): truncated value with size 32 to match size of target (8)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1228): truncated value with size 32 to match size of target (5)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1233): truncated value with size 32 to match size of target (5)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1284): truncated value with size 32 to match size of target (3)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1324): truncated value with size 10 to match size of target (6)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1326): truncated value with size 32 to match size of target (6)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1333): truncated value with size 32 to match size of target (6)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1335): truncated value with size 32 to match size of target (6)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1344): truncated value with size 32 to match size of target (2)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(829): truncated value with size 32 to match size of target (5)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(832): truncated value with size 32 to match size of target (5)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at nmcounter.v(169): truncated value with size 32 to match size of target (25)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at nmcounter.v(220): truncated value with size 32 to match size of target (6)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at nmcounter.v(222): truncated value with size 32 to match size of target (6)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at nmcounter.v(304): truncated value with size 32 to match size of target (16)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(21): truncated value with size 32 to match size of target (6)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(24): truncated value with size 32 to match size of target (6)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(27): truncated value with size 32 to match size of target (4)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(28): truncated value with size 32 to match size of target (30)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(39): truncated value with size 30 to match size of target (12)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(97): truncated value with size 32 to match size of target (4)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(256): truncated value with size 32 to match size of target (8)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(258): truncated value with size 32 to match size of target (8)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(71): truncated value with size 32 to match size of target (3)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(152): truncated value with size 32 to match size of target (10)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(173): truncated value with size 32 to match size of target (10)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (5)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (10)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at ms5540c.v(134): truncated value with size 32 to match size of target (11)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at ms5540c.v(136): truncated value with size 32 to match size of target (11)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at ms5540c.v(149): truncated value with size 32 to match size of target (12)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at ms5540c.v(159): truncated value with size 32 to match size of target (8)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at ms5540c.v(206): truncated value with size 32 to match size of target (5)
quartus/irenacore.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (16)
quartus/irenacore.map.rpt:Warning (12241): 6 hierarchies have connectivity warnings - see the Connectivity Checks report folder
quartus/irenacore.map.rpt:Warning (15899): PLL "pll96:pll0|altpll:altpll_component|altpll_lm43:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
quartus/irenacore.map.rpt:Warning (21074): Design contains 2 input pin(s) that do not drive logic
quartus/irenacore.map.rpt:    Warning (15610): No output dependent on input pin "clk_T1"
quartus/irenacore.map.rpt:    Warning (15610): No output dependent on input pin "trigger"
quartus/irenacore.map.rpt:Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 77 warnings
quartus/irenacore.sta.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/irenacore.sta.rpt:Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning