quartus/pirena.asm.rpt:Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings quartus/pirena.fit.rpt: 5. I/O Assignment Warnings quartus/pirena.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; quartus/pirena.fit.rpt:; I/O Assignment Warnings ; quartus/pirena.fit.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled quartus/pirena.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. quartus/pirena.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details quartus/pirena.fit.rpt:Warning (176674): Following 7 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins. quartus/pirena.fit.rpt: Warning (176118): Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)" quartus/pirena.fit.rpt: Warning (176118): Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)" quartus/pirena.fit.rpt: Warning (176118): Pin "FE_clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "FE_clk(n)" quartus/pirena.fit.rpt: Warning (176118): Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)" quartus/pirena.fit.rpt: Warning (176118): Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)" quartus/pirena.fit.rpt: Warning (176118): Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)" quartus/pirena.fit.rpt: Warning (176118): Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)" quartus/pirena.fit.rpt:Info: Quartus II 32-bit Fitter was successful. 0 errors, 11 warnings quartus/pirena.map.rpt:; conf3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; quartus/pirena.map.rpt:; fifo_empty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; quartus/pirena.map.rpt:; c1 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; quartus/pirena.map.rpt:; c2 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; quartus/pirena.map.rpt:; c3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; quartus/pirena.map.rpt:; c4 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; quartus/pirena.map.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled quartus/pirena.map.rpt:Warning (10034): Output port "test" at pirena.v(14) has no driver quartus/pirena.map.rpt:Warning (10034): Output port "spare" at pirena.v(15) has no driver quartus/pirena.map.rpt:Warning (10034): Output port "debug" at pirena.v(16) has no driver quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(97): truncated value with size 32 to match size of target (4) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(256): truncated value with size 32 to match size of target (8) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(258): truncated value with size 32 to match size of target (8) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(70): truncated value with size 32 to match size of target (3) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(151): truncated value with size 32 to match size of target (10) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(172): truncated value with size 32 to match size of target (10) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (5) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (10) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at trigen.v(29): truncated value with size 32 to match size of target (16) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at trigen.v(48): truncated value with size 32 to match size of target (12) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at trigen.v(50): truncated value with size 32 to match size of target (12) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at trigen.v(58): truncated value with size 32 to match size of target (16) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ad7690.v(195): truncated value with size 32 to match size of target (4) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ad7690.v(234): truncated value with size 32 to match size of target (7) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ad7690.v(274): truncated value with size 32 to match size of target (16) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ad7690.v(274): truncated value with size 32 to match size of target (8) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ad7690.v(104): truncated value with size 32 to match size of target (4) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ad7690.v(18): truncated value with size 32 to match size of target (8) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ad7690.v(20): truncated value with size 32 to match size of target (8) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ad7690.v(144): truncated value with size 32 to match size of target (16) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ltc2656.v(41): truncated value with size 32 to match size of target (10) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ltc2656.v(43): truncated value with size 32 to match size of target (10) quartus/pirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ltc2656.v(45): truncated value with size 32 to match size of target (10) quartus/pirena.map.rpt:Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder quartus/pirena.map.rpt:Warning (13024): Output pins are stuck at VCC or GND quartus/pirena.map.rpt: Warning (13410): Pin "test[0]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "test[1]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "test[2]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[0]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[1]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[2]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[3]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[4]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[5]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[6]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[7]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[8]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[9]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[10]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[11]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[12]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[13]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[14]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[15]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[16]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[17]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "spare[18]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "debug[0]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "debug[1]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "debug[2]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "debug[3]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "debug[4]" is stuck at GND quartus/pirena.map.rpt: Warning (13410): Pin "debug[5]" is stuck at GND quartus/pirena.map.rpt:Warning (15899): PLL "pll96:pll0|altpll:altpll_component|altpll_lm43:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected quartus/pirena.map.rpt:Warning (21074): Design contains 2 input pin(s) that do not drive logic quartus/pirena.map.rpt: Warning (15610): No output dependent on input pin "clk_T1" quartus/pirena.map.rpt: Warning (15610): No output dependent on input pin "FE_clk" quartus/pirena.map.rpt:Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 62 warnings quartus/pirena.sta.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled quartus/pirena.sta.rpt:Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning