VERILOG=/usr/local/bin/iverilog
#VERILOG=/usr/bin/iverilog

VERILOGFLAGS = -v -Wall -Wno-timescale -DSIMULATION $($*_FLAGS) $(IVLFLAGS)
%.vvp:
	$(VERILOG) $(VERILOGFLAGS) -o $@ $(filter %.v, $^)

vcd/%.lxt: %.vvp
	$< -lxt2 | tee $*.log

.PRECIOUS: vcd/%.lxt

VPATH=.:./l3:./encode:./hk:../../flyrena/altera:../../hetept/altera:../../altera:\
../../altera/mega:../../altera/actel:../../stein/altera:\
../../sirena/altera:../../cospi/altera

SPWIRENA_DEFS = -DSPWIRENA_CORE2=1
spwirena_FLAGS = -s spwirena_test -DSPWIRENA_TEST -DSpW_TEST -DSPWIRENA_CORE=1 $(SPWIRENA_DEFS)

spwirena.vvp: spwirena.v  spwirena_core.v  SpW.v \
 frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
 frontend_test.v fifo8_sim.v serializer.v

SPW_SOLOGSE_DEFS = 
spw_sologse_FLAGS = -s spw_sologse_test -DSOLOGSE48 -DSPW_SOLOGSE_TEST $(SPWIRENA_DEFS)

spw_sologse.vvp: spwirena.v sologse48.v  \
 icucore.v uart.v memory.v secondcyclone.v serializer.v \
 frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
 frontend_test.v fifo8_sim.v


QUARTUS=/usr/local/quartus/altera13.1/quartus
export PATH:=$(PATH):$(QUARTUS)/bin

QDIR=quartus

$(QDIR)/%.rbf: %.qpf %.qsf %.sdc
	rm -rf db incremental_db
	quartus_map $<
	quartus_fit $<
	quartus_asm $<
	quartus_sta $<
	grep -i warning $(QDIR)/$*.*.rpt > $*.warnings

FRONTEND = conf_reg.v spi_slave.v pll384.v spififo.v frontend.v packetfifo.v

$(QDIR)/spwirena.rbf: spwirena.v $(FRONTEND) spwirena_core.v SpW.v
$(QDIR)/spwsologse.rbf: spwirena.v $(FRONTEND) sologse48.v icucore.v 
$(QDIR)/spwce4gse.rbf: spwirena.v $(FRONTEND) sologse48.v icucore.v 

clean:
	rm -rf db incremental_db *.vvp