VERILOG=/usr/local/bin/iverilog
#VERILOG=/usr/bin/iverilog

VERILOGFLAGS = -v -DSIMULATION $($*_FLAGS)
%.vvp: 
	$(VERILOG) $(VERILOGFLAGS) -o $@ $(filter %.v,$^)

vcd/%.fst: %.vvp
	$< -fst | tee $*.log

.PRECIOUS: vcd/%.fst

VPATH=.:./virena:./idef-x:./sixs:./adc128:../../altera:../../altera/mega\
:../../stein/altera:../../dorn/altera:../../nm64/altera/\
:../../ahepam/altera:../../dorn/altera:../../irena/altera/adc128

varena_FLAGS = -DVARENA -s varena_test
iarena_FLAGS = -DIARENA -s iarena_test -DNOINVTRIG 
tarena_FLAGS = -DTARENA -s tarena_test -DARxSTREAM
sarena_FLAGS = -DSARENA -s sarena_test
aarena_FLAGS = -DAARENA -s aarena_test -DAARENA_TEST
harena_FLAGS = -DHARENA -s harena_test -DHARENA_TEST -DAHEPAM_ANA_JIG \
  -DINFERRED_SRAM -DSER_FIFO_ALTERA \
  -DWITH_FULL_L1_CONF -DWITH_FULL_L2_CONF -DWITH_FULL_L3_CONF

varena.vvp: arena.v varena.v \
 frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v \
 varena_test.v virena_sim.v ad9649.v frontend_test.v \
 varena.v virena_conf.v vl1trig.v vl2trig.v vl3trig.v \
 adc_data.v logicanalyser.v oscilloscope.v testpulser.v \
 confmem.v spi_master_adc.v

iarena.vvp: arena.v iarena.v \
 frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
 iarena_test.v ad9649.v frontend_test.v \
 iarena.v ix.v \
 adc_data.v lasc.v fifo16.v  testpulser.v spi_master_adc.v

tarena.vvp: arena.v tarena.v\
 frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
 tarena_test.v ad9649.v frontend_test.v \
 tarena.v ix.v \
 adc_data.v logicanalyser.v oscilloscope.v testpulser.v spi_master_adc.v \
 stein_adc_controller.v stein_ix_controller.v stein_l2trig.v stein_channel_map.v \
 serializer.v adc128s102.v priority_encoder.v barrel.v

sarena.vvp:  sarena_test.v arena.v sarena.v sixs.v \
 frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v \
 ad9649.v frontend_test.v \
 adc_data.v logicanalyser.v oscilloscope.v testpulser.v spi_master_adc.v

aarena.vvp:  arena.v aarena.v secondcyclone.v serializer.v \
 frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
 ad9649.v frontend_test.v \
 adc_data.v oscilloscope.v spi_master_adc.v

harena.vvp:  arena.v aarena.v secondcyclone.v serializer.v \
 frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
 ad9649.v frontend_test.v \
 adc_data.v oscilloscope.v spi_master_adc.v \
 ahepam_ana_demo.v ahepam_ana_core.v \
 itof.v \
 adc128s102.v mem.v \
 dorn.v dmem.v divider.v multiply.v \
 pulser.v \
 sallen-key-pulse.hex

QDIR=quartus
QUARTUS=/usr/local/quartus/altera13.1/quartus
export PATH:=$(PATH):$(QUARTUS)/bin

MAPFLGS = $(patsubst %, --verilog_macro="%",$($*_MAPDEFS))

$(QDIR)/%.rbf: %.qpf %.qsf %.sdc
	quartus_map $< $(MAPFLGS)
	quartus_fit $<
	quartus_asm $<
	quartus_sta $<
	grep -i warning $(QDIR)/$*.*.rpt > $*.warnings

arena.rbf: arena.v

FRONTEND = conf_reg.v spi_slave.v pll96.v spififo.v frontend.v packetfifo.v countbits.v

$(QDIR)/varena.rbf: varena.v spi_master_adc.v \
	  $(FRONTEND) \
	  arena.v confmem.v sram256x32.v adc_data.v oscilloscope.v \
	  virena_conf.v vl1trig.v vl2trig.v vl3trig.v

$(QDIR)/iarena.rbf: iarena.v spi_master_adc.v \
	  $(FRONTEND) \
	  arena.v adc_data.v lasc.v fifo16.v  \
	  ix.v

$(QDIR)/tarena.rbf: tarena.v spi_master_adc.v \
	  $(FRONTEND) \
	  arena.v adc_data.v oscilloscope.v logicanalyser.v testpulser.v  spi_master_adc.v \
	  stein_adc_controller.v stein_ix_controller.v stein_l2trig.v \
	  ix.v serializer.v adc128s102.v priority_encoder.v barrel.v

$(QDIR)/iarenait.rbf:
	rm -f $(QDIR)/iarena.rbf
	$(MAKE) iarena_MAPDEFS='NOINVTRIG=1' $(QDIR)/iarena.rbf
	mv $(QDIR)/iarena.rbf $@

$(QDIR)/sarena.rbf: sarena.v spi_master_adc.v \
	  $(FRONTEND) \
	  arena.v adc_data.v oscilloscope.v \
	  sixs.v

$(QDIR)/aarena.rbf: arena.v aarena.v \
	  $(FRONTEND) \
	  spi_master_adc.v adc_data.v oscilloscope.v \
	  secondcyclone.v serializer.v pll240_96.v pll240d_96.v

$(QDIR)/harena.rbf: arena.v aarena.v \
	  $(FRONTEND) \
	  spi_master_adc.v adc_data.v oscilloscope.v \
	  secondcyclone.v serializer.v

$(QDIR)/narena.rbf: arena.v aarena.v \
	  $(FRONTEND) stis_ana_core.v \
	  spi_master_adc.v adc_data.v oscilloscope.v \
	  secondcyclone.v serializer.v

$(QDIR)/darena.rbf: darena.v dorn.v dmem.v dornpulse.v divider.v adc128s102.v ltc2656.v \
	  $(FRONTEND) \
	  arena.v pll96.v spi_master_adc.v adc_data.v oscilloscope.v