b18ab4a5c9
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@6133 bc5caf13-1734-44f8-af43-603852e9ee25
54 lines
1.6 KiB
Makefile
54 lines
1.6 KiB
Makefile
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VERILOG=/usr/local/bin/iverilog
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#VERILOG=/usr/bin/iverilog
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VERILOGFLAGS = -v -Wall -Wno-timescale -DSIMULATION $($*_FLAGS) $(IVLFLAGS)
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%.vvp:
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$(VERILOG) $(VERILOGFLAGS) -o $@ $(filter %.v, $^)
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vcd/%.lxt: %.vvp
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$< -lxt2 | tee $*.log
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.PRECIOUS: vcd/%.lxt
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VPATH=.:./l3:./encode:./hk:../../flyrena/altera:../../hetept/altera:../../altera:\
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../../altera/mega:../../altera/actel:../../stein/altera:\
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../../sirena/altera:../../cospi/altera
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SPWIRENA_DEFS = -DSPWIRENA_CORE2=1
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spwirena_FLAGS = -s spwirena_test -DSPWIRENA_TEST -DSpW_TEST -DSPWIRENA_CORE=1 $(SPWIRENA_DEFS)
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spwirena.vvp: spwirena.v spwirena_core.v SpW.v \
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frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
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frontend_test.v fifo8_sim.v serializer.v
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SPW_SOLOGSE_DEFS =
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spw_sologse_FLAGS = -s spw_sologse_test -DSOLOGSE48 -DSPW_SOLOGSE_TEST $(SPWIRENA_DEFS)
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spw_sologse.vvp: spwirena.v sologse48.v \
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icucore.v uart.v memory.v secondcyclone.v serializer.v \
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frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
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frontend_test.v fifo8_sim.v
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QUARTUS=/usr/local/quartus/altera13.1/quartus
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export PATH:=$(PATH):$(QUARTUS)/bin
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QDIR=quartus
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$(QDIR)/%.rbf: %.qpf %.qsf %.sdc
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rm -rf db incremental_db
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quartus_map $<
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quartus_fit $<
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quartus_asm $<
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quartus_sta $<
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grep -i warning $(QDIR)/$*.*.rpt > $*.warnings
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FRONTEND = conf_reg.v spi_slave.v pll384.v spififo.v frontend.v packetfifo.v
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$(QDIR)/spwirena.rbf: spwirena.v $(FRONTEND) spwirena_core.v SpW.v
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$(QDIR)/spwsologse.rbf: spwirena.v $(FRONTEND) sologse48.v icucore.v
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$(QDIR)/spwce4gse.rbf: spwirena.v $(FRONTEND) sologse48.v icucore.v
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clean:
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rm -rf db incremental_db *.vvp
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