solo_altera/altera
2026-03-25 20:13:30 +01:00
..
actel merge C'E4 tuning into trunc 2017-03-17 20:56:45 +00:00
mega nmleia_c3: pinout for nmrena_v1 board 2025-11-05 19:55:31 +00:00
ad9251_data.v ccdrena: support for recent development 2013-09-16 21:25:06 +00:00
adc128s102.v move net decls before use 2026-03-16 22:23:47 +01:00
adc_bit.v move adc driver to altera lib 2011-08-03 09:19:49 +00:00
barrel.v removed anachronistic expression 2014-03-13 14:22:37 +00:00
conf_reg.v conf_reg: fix for target altera 2024-02-26 18:36:01 +00:00
conf_reg_test.v move common files from erena/altera to new lib dir 2011-05-17 06:43:32 +00:00
countbits.v countbits: balanced adder tree implementation, quartus is much happier 2016-12-06 21:11:04 +00:00
fifo8_sim.v move common files from erena/altera to new lib dir 2011-05-17 06:43:32 +00:00
fifo16n.v iarena lasc: use a previous fifo16 implementation 2021-03-20 11:03:57 +00:00
frontend.v frontend: properly wire up lost_sync 2026-03-16 08:17:17 +01:00
frontend_test.v spi_test: detect, flag and mitigate frame collisions 2025-03-02 20:06:21 +00:00
i2c.gold i2c: go_unstuck 2024-12-29 13:58:33 +00:00
i2c.gtkw i2cm: runs well, with abort, from spififo 2024-12-30 10:52:28 +00:00
i2c.v i2cm_jig: testjig module for I²C 2025-03-02 20:07:41 +00:00
i2cm.gold i2cm_jig: testjig module for I²C 2025-03-02 20:07:41 +00:00
i2cm.gtkw i2cm: gtkw 2025-01-16 22:44:21 +00:00
itof.v itof: Fix BUG in itouf 2015-01-13 23:14:02 +00:00
lasc.gold LASC: unified logic analyser ans oscilloscope 2021-03-19 21:55:39 +00:00
lasc.gtkw LASC: unified logic analyser ans oscilloscope 2021-03-19 21:55:39 +00:00
lasc.v lasc: sim diagnostic waveforms 2021-03-21 17:02:23 +00:00
logicanalyser.v lana: status readback 2025-11-09 13:20:03 +00:00
Makefile i2cm: runs well, with abort, from spififo 2024-12-30 10:52:28 +00:00
mem.v comment typo 2019-10-15 18:25:20 +00:00
packetfifo.v packetfifo: be afull earlier 2024-07-20 20:20:45 +00:00
pll192_sim.v pll192_test 2024-10-15 13:59:10 +00:00
pll192_test.v nmahepam: mclk=64MHz, resets[0]=plltest reset 2024-10-17 12:05:43 +00:00
por.v hetept por: self init message 2018-11-21 14:36:11 +00:00
priority_encoder.v added testjig for barrel and priority-encoder combi-test 2013-07-17 09:37:51 +00:00
README.txt better use GPL2, I must not grant CAU patent licenses 2011-05-17 08:19:31 +00:00
scangen.v nm_mcs: seems to work 2020-02-18 20:49:23 +00:00
secondcyclone.v secondcyclone: add fifo size parameters to ser_slave_tx 2024-02-23 09:05:50 +00:00
serializer.gold serializer: old gold 2017-03-15 16:29:07 +00:00
serializer.gtkw serializer split: 4x oversampling 2013-12-18 10:15:38 +00:00
serializer.v spw_sologse: tweaks for f2 timing, ARxC 2017-02-17 23:09:08 +00:00
slow_clock.gtkw slow_clock: module sclk_to_fclk() 2024-10-23 14:06:16 +00:00
slow_clock.v slow_clock: module sclk_to_fclk() 2024-10-23 14:06:16 +00:00
spi_master_adc.v both fpgas sim and synth 2012-02-04 12:30:29 +00:00
spi_slave.v spi_slave_timeout: support 1024 cycle long timeout 2026-03-25 20:13:30 +01:00
spi_slave_test.v move common files from erena/altera to new lib dir 2011-05-17 06:43:32 +00:00
spififo_sim.v kludge for fixing corrupted state of spi_fifo at statup 2012-08-04 16:04:16 +00:00
spififo_test.v move common files from erena/altera to new lib dir 2011-05-17 06:43:32 +00:00
SpW.gold SpW: gold for EEP/EoP fix 2019-01-28 16:53:34 +00:00
SpW.gtkw SpW: fix parity 2016-11-21 23:22:47 +00:00
SpW.v SpW: 2019-11-24 20:52:55 +00:00
SpW3.gold SpW3 gold 2019-03-21 21:38:29 +00:00
SpW3.gtkw SpW: serialize EOP with nChar, i.e., feed EOP through nchar_req, level3 simulation 2016-11-23 13:24:50 +00:00
utick.v utick_test 2024-09-24 11:21:02 +00:00

This program provides common HDL modules for the IRENA family of data
acquisition instruments that are develeoped and used at the Institute
for Experimantal and Applied Physics at the Christian-Albrechts-
University in Kiel, Germany.

Copyright (c) 2010-2011 Christian-Albrechts-Universität zu Kiel
Copyright (c) 2010-2011 Stephan Böttcher

This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or (at
your option) any later version.

This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.


The files in the mega/ subdirectory are Copyright (c) by Altera and
are not covered by this license.  You/we may not be allowed to
distribute those, but I could not settle that question by reading the
Altera license.  The megafunctions provide access to hardware blocks
of the specific FPGA (Cyclon 3), pll, sram, multiplier.  They were
made with a Quartus II web-edition, and do not contain much except for
descriptions of the interface to these functions.

In the context of this program, the megafunctions fall under the
clause of libraries that are part of the _operating system_.  You may
distribute derived works of this program according to this licecnse,
that use similar megafunctions for this or other targets, as long as
these megafunctions are simple interface descriptions to facilities
that are provided as hardwired components by the target.  E.g., this
does not cover proprietary CPUs or similar modules, which are
synthesized from generic logic cells.