45f97b5aa6
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@9398 bc5caf13-1734-44f8-af43-603852e9ee25
129 lines
4.3 KiB
Makefile
129 lines
4.3 KiB
Makefile
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VERILOG=/usr/local/bin/iverilog
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#VERILOG=/usr/bin/iverilog
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VERILOGFLAGS = -v -DSIMULATION $($*_FLAGS)
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%.vvp:
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$(VERILOG) $(VERILOGFLAGS) -o $@ $(filter %.v,$^)
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vcd/%.fst: %.vvp
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$< -fst | tee $*.log
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.PRECIOUS: vcd/%.fst
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VPATH=.:./virena:./idef-x:./sixs:./adc128:../../altera:../../altera/mega\
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:../../stein/altera:../../dorn/altera:../../nm64/altera/\
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:../../ahepam/altera:../../dorn/altera:../../irena/altera/adc128
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varena_FLAGS = -DVARENA -s varena_test
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iarena_FLAGS = -DIARENA -s iarena_test -DNOINVTRIG
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tarena_FLAGS = -DTARENA -s tarena_test -DARxSTREAM
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sarena_FLAGS = -DSARENA -s sarena_test
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aarena_FLAGS = -DAARENA -s aarena_test -DAARENA_TEST
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harena_FLAGS = -DHARENA -s harena_test -DHARENA_TEST -DAHEPAM_ANA_JIG \
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-DINFERRED_SRAM -DSER_FIFO_ALTERA \
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-DWITH_FULL_L1_CONF -DWITH_FULL_L2_CONF -DWITH_FULL_L3_CONF
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varena.vvp: arena.v varena.v \
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frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v \
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varena_test.v virena_sim.v ad9649.v frontend_test.v \
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varena.v virena_conf.v vl1trig.v vl2trig.v vl3trig.v \
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adc_data.v logicanalyser.v oscilloscope.v testpulser.v \
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confmem.v spi_master_adc.v
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iarena.vvp: arena.v iarena.v \
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frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
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iarena_test.v ad9649.v frontend_test.v \
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iarena.v ix.v \
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adc_data.v lasc.v fifo16.v testpulser.v spi_master_adc.v
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tarena.vvp: arena.v tarena.v\
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frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
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tarena_test.v ad9649.v frontend_test.v \
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tarena.v ix.v \
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adc_data.v logicanalyser.v oscilloscope.v testpulser.v spi_master_adc.v \
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stein_adc_controller.v stein_ix_controller.v stein_l2trig.v stein_channel_map.v \
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serializer.v adc128s102.v priority_encoder.v barrel.v
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sarena.vvp: sarena_test.v arena.v sarena.v sixs.v \
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frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v \
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ad9649.v frontend_test.v \
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adc_data.v logicanalyser.v oscilloscope.v testpulser.v spi_master_adc.v
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aarena.vvp: arena.v aarena.v secondcyclone.v serializer.v \
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frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
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ad9649.v frontend_test.v \
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adc_data.v oscilloscope.v spi_master_adc.v
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harena.vvp: arena.v aarena.v secondcyclone.v serializer.v \
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frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
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ad9649.v frontend_test.v \
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adc_data.v oscilloscope.v spi_master_adc.v \
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ahepam_ana_demo.v ahepam_ana_core.v \
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itof.v \
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adc128s102.v mem.v \
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dorn.v dmem.v divider.v multiply.v \
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pulser.v \
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sallen-key-pulse.hex
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QDIR=quartus
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QUARTUS=/usr/local/quartus/altera13.1/quartus
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export PATH:=$(PATH):$(QUARTUS)/bin
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MAPFLGS = $(patsubst %, --verilog_macro="%",$($*_MAPDEFS))
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$(QDIR)/%.rbf: %.qpf %.qsf %.sdc
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quartus_map $< $(MAPFLGS)
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quartus_fit $<
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quartus_asm $<
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quartus_sta $<
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grep -i warning $(QDIR)/$*.*.rpt > $*.warnings
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arena.rbf: arena.v
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FRONTEND = conf_reg.v spi_slave.v pll96.v spififo.v frontend.v packetfifo.v countbits.v
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$(QDIR)/varena.rbf: varena.v spi_master_adc.v \
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$(FRONTEND) \
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arena.v confmem.v sram256x32.v adc_data.v oscilloscope.v \
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virena_conf.v vl1trig.v vl2trig.v vl3trig.v
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$(QDIR)/iarena.rbf: iarena.v spi_master_adc.v \
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$(FRONTEND) \
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arena.v adc_data.v lasc.v fifo16.v \
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ix.v
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$(QDIR)/tarena.rbf: tarena.v spi_master_adc.v \
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$(FRONTEND) \
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arena.v adc_data.v oscilloscope.v logicanalyser.v testpulser.v spi_master_adc.v \
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stein_adc_controller.v stein_ix_controller.v stein_l2trig.v \
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ix.v serializer.v adc128s102.v priority_encoder.v barrel.v
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$(QDIR)/iarenait.rbf:
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rm -f $(QDIR)/iarena.rbf
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$(MAKE) iarena_MAPDEFS='NOINVTRIG=1' $(QDIR)/iarena.rbf
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mv $(QDIR)/iarena.rbf $@
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$(QDIR)/sarena.rbf: sarena.v spi_master_adc.v \
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$(FRONTEND) \
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arena.v adc_data.v oscilloscope.v \
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sixs.v
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$(QDIR)/aarena.rbf: arena.v aarena.v \
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$(FRONTEND) \
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spi_master_adc.v adc_data.v oscilloscope.v \
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secondcyclone.v serializer.v pll240_96.v pll240d_96.v
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$(QDIR)/harena.rbf: arena.v aarena.v \
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$(FRONTEND) \
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spi_master_adc.v adc_data.v oscilloscope.v \
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secondcyclone.v serializer.v
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$(QDIR)/narena.rbf: arena.v aarena.v \
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$(FRONTEND) stis_ana_core.v \
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spi_master_adc.v adc_data.v oscilloscope.v \
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secondcyclone.v serializer.v
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$(QDIR)/darena.rbf: darena.v dorn.v dmem.v dornpulse.v divider.v adc128s102.v ltc2656.v \
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$(FRONTEND) \
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arena.v pll96.v spi_master_adc.v adc_data.v oscilloscope.v
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