3b4fa9b1b3
fix bitrot location of module countbits ports of module frontend consistently use fifo_halffull[2] git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5290 bc5caf13-1734-44f8-af43-603852e9ee25
45 lines
6.1 KiB
Text
45 lines
6.1 KiB
Text
cecederena.asm.rpt:Info: Quartus II Assembler was successful. 0 errors, 0 warnings
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cecederena.fit.rpt: 5. I/O Assignment Warnings
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cecederena.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
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cecederena.fit.rpt:; I/O Assignment Warnings ;
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cecederena.fit.rpt:Warning: Implemented PLL "pll240:pll0|altpll:altpll_component|altpll_j203:auto_generated|pll1" as Cyclone III PLL type, but with warnings
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cecederena.fit.rpt: Warning: Can't achieve requested value 86.4 degrees for clock output pll240:pll0|altpll:altpll_component|altpll_j203:auto_generated|clk[3] of parameter phase shift -- achieved value of 90.0 degrees
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cecederena.fit.rpt:Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.
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cecederena.fit.rpt:Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
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cecederena.fit.rpt:Warning: Following 8 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
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cecederena.fit.rpt: Warning: Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)"
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cecederena.fit.rpt: Warning: Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)"
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cecederena.fit.rpt: Warning: Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)"
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cecederena.fit.rpt: Warning: Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
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cecederena.fit.rpt: Warning: Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
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cecederena.fit.rpt: Warning: Pin "SRx[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "SRx[1](n)"
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cecederena.fit.rpt: Warning: Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
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cecederena.fit.rpt: Warning: Pin "SRx[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "SRx[2](n)"
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cecederena.fit.rpt:Warning: Reference pin STxp[1] is invalid. It is not clocked by the clock specified in set_input_delay/set_output_delay's -clock option.
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cecederena.fit.rpt:Info: Quartus II Fitter was successful. 0 errors, 14 warnings
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cecederena.map.rpt:; halffull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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cecederena.map.rpt:; c1 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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cecederena.map.rpt:; c2 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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cecederena.map.rpt:; c3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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cecederena.map.rpt:; c4 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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cecederena.map.rpt:; c1 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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cecederena.map.rpt:; c2 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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cecederena.map.rpt:; c4 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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cecederena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/serializer.v(188)
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cecederena.map.rpt:Warning (10296): VHDL warning at pll240.vhd(194): ignored assignment of value to null range
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cecederena.map.rpt:Warning (10296): VHDL warning at pll240d.vhd(194): ignored assignment of value to null range
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cecederena.map.rpt:Warning: 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
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cecederena.map.rpt:Warning: Output pins are stuck at VCC or GND
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cecederena.map.rpt: Warning (13410): Pin "debug[3]" is stuck at GND
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cecederena.map.rpt: Warning (13410): Pin "debug[2]" is stuck at GND
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cecederena.map.rpt: Warning (13410): Pin "debug[1]" is stuck at GND
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cecederena.map.rpt:Warning: PLL "pll240:pll0|altpll:altpll_component|altpll_j203:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
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cecederena.map.rpt:Warning: PLL "pll240d:pll1|altpll:altpll_component|altpll_dpv2:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
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cecederena.map.rpt:Warning: Reference pin STxp[1] is invalid. It is not clocked by the clock specified in set_input_delay/set_output_delay's -clock option.
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cecederena.map.rpt:Warning: PLL "pll240:pll0|altpll:altpll_component|altpll_j203:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
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cecederena.map.rpt:Warning: Design contains 2 input pin(s) that do not drive logic
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cecederena.map.rpt: Warning (15610): No output dependent on input pin "clk_T1"
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cecederena.map.rpt: Warning (15610): No output dependent on input pin "trigger"
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cecederena.map.rpt:Info: Quartus II Analysis & Synthesis was successful. 0 errors, 47 warnings
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cecederena.sta.rpt:Warning: Reference pin STxp[1] is invalid. It is not clocked by the clock specified in set_input_delay/set_output_delay's -clock option.
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cecederena.sta.rpt:Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 1 warning
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