9b1e605578
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2456 bc5caf13-1734-44f8-af43-603852e9ee25
144 lines
19 KiB
Text
144 lines
19 KiB
Text
rpirena.asm.rpt:Info: Quartus II Assembler was successful. 0 errors, 0 warnings
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rpirena.fit.rpt: 5. I/O Assignment Warnings
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rpirena.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
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rpirena.fit.rpt:; I/O Assignment Warnings ;
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rpirena.fit.rpt:Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.
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rpirena.fit.rpt:Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
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rpirena.fit.rpt:Warning: Following 4 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
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rpirena.fit.rpt: Warning: Pin "LRx[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRx[2](n)"
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rpirena.fit.rpt: Warning: Pin "LRx[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRx[1](n)"
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rpirena.fit.rpt: Warning: Pin "LRTx[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRTx[2](n)"
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rpirena.fit.rpt: Warning: Pin "LRTx[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRTx[1](n)"
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rpirena.fit.rpt:Warning: 33 pins must meet Altera requirements for 3.3, 3.0, and 2.5-V interfaces. Refer to the device Application Note 447 (Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems).
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rpirena.fit.rpt:Warning: PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447.
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rpirena.fit.rpt:Warning: Following 12 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
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rpirena.fit.rpt:Info: Quartus II Fitter was successful. 0 errors, 10 warnings
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rpirena.map.rpt:; dout1 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpirena.map.rpt:; dine ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpirena.map.rpt:; n ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpirena.map.rpt:; rro ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpirena.map.rpt:; rro ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpirena.map.rpt:; rrn ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (7 bits) it drives. The 25 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
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rpirena.map.rpt:; rro ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpirena.map.rpt:; a ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpirena.map.rpt:; b ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpirena.map.rpt:; apeak ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpirena.map.rpt:; bzero ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpirena.map.rpt:; rbi ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
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rpirena.map.rpt:; halffull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpirena.map.rpt:; attn ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpirena.map.rpt:; c1 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpirena.map.rpt:; c2 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpirena.map.rpt:; c3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpirena.map.rpt:; c4 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpirena.map.rpt:Warning (10229): Verilog HDL Expression warning at irena_core.v(263): truncated literal to match 14 bits
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rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(36): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(37): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(38): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(39): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(40): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(41): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(42): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(50): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(51): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(52): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(80): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(81): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(82): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(83): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(85): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at irena_core.v(86): Parameter Declaration in module "irenacore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at adccntl.v(140): Parameter Declaration in module "adc_channels" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at rpirena.v(150): truncated value with size 32 to match size of target (27)
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rpirena.map.rpt:Warning (10034): Output port "LTxP" at rpirena.v(23) has no driver
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rpirena.map.rpt:Warning (10034): Output port "LTxN" at rpirena.v(24) has no driver
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(97): truncated value with size 32 to match size of target (4)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(253): truncated value with size 32 to match size of target (8)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(255): truncated value with size 32 to match size of target (8)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(83): truncated value with size 32 to match size of target (3)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(137): truncated value with size 32 to match size of target (10)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at irena_core.v(76): truncated value with size 32 to match size of target (16)
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rpirena.map.rpt:Warning (10036): Verilog HDL or VHDL warning at adccntl.v(116): object "phmm" assigned a value but never read
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at adccntl.v(118): truncated value with size 32 to match size of target (6)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(707): truncated value with size 32 to match size of target (7)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(745): truncated value with size 32 to match size of target (5)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(760): truncated value with size 32 to match size of target (10)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1337): truncated value with size 32 to match size of target (7)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1342): truncated value with size 32 to match size of target (7)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1359): truncated value with size 30 to match size of target (16)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(826): truncated value with size 32 to match size of target (4)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(853): truncated value with size 32 to match size of target (4)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(855): truncated value with size 32 to match size of target (4)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(889): truncated value with size 32 to match size of target (16)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(911): truncated value with size 32 to match size of target (8)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(928): truncated value with size 32 to match size of target (5)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(930): truncated value with size 32 to match size of target (5)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(975): truncated value with size 32 to match size of target (4)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at irena_core.v(273): truncated value with size 32 to match size of target (5)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1010): truncated value with size 32 to match size of target (8)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1017): truncated value with size 32 to match size of target (6)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1019): truncated value with size 32 to match size of target (6)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1028): truncated value with size 32 to match size of target (2)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(628): truncated value with size 32 to match size of target (5)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(631): truncated value with size 32 to match size of target (5)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1410): truncated value with size 3 to match size of target (2)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1414): truncated value with size 4 to match size of target (3)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1416): truncated value with size 4 to match size of target (3)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at sfilter.v(1423): truncated value with size 32 to match size of target (5)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(21): truncated value with size 32 to match size of target (6)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(24): truncated value with size 32 to match size of target (6)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(27): truncated value with size 32 to match size of target (4)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(28): truncated value with size 32 to match size of target (30)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(39): truncated value with size 30 to match size of target (12)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at hkadc.v(41): truncated value with size 32 to match size of target (3)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at hkadc.v(100): truncated value with size 32 to match size of target (3)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at adc128s102.v(102): truncated value with size 32 to match size of target (4)
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rpirena.map.rpt:Warning (10230): Verilog HDL assignment warning at rpirena.v(172): truncated value with size 32 to match size of target (7)
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rpirena.map.rpt:Warning: 10 hierarchies have connectivity warnings - see the Connectivity Checks report folder
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rpirena.map.rpt:Warning: The following nodes have both tri-state and non-tri-state drivers
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rpirena.map.rpt: Warning: Inserted always-enabled tri-state buffer between "PP[0]" and its non-tri-state driver.
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rpirena.map.rpt: Warning: Inserted always-enabled tri-state buffer between "PP[1]" and its non-tri-state driver.
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rpirena.map.rpt: Warning: Inserted always-enabled tri-state buffer between "PP[2]" and its non-tri-state driver.
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rpirena.map.rpt:Warning: The following bidir pins have no drivers
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rpirena.map.rpt: Warning: Bidir "gpio17" has no driver
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rpirena.map.rpt: Warning: Bidir "gpio22" has no driver
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rpirena.map.rpt: Warning: Bidir "gpio27" has no driver
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rpirena.map.rpt: Warning: Bidir "gpclk0" has no driver
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rpirena.map.rpt: Warning: Bidir "SCL" has no driver
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rpirena.map.rpt: Warning: Bidir "SDA" has no driver
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rpirena.map.rpt: Warning: Bidir "PP[3]" has no driver
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rpirena.map.rpt: Warning: Bidir "PP[4]" has no driver
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rpirena.map.rpt: Warning: Bidir "PP[5]" has no driver
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rpirena.map.rpt:Warning: TRI or OPNDRN buffers permanently enabled
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rpirena.map.rpt: Warning: Node "PP[0]~synth"
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rpirena.map.rpt: Warning: Node "PP[1]~synth"
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rpirena.map.rpt: Warning: Node "PP[2]~synth"
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rpirena.map.rpt:Warning: Output pins are stuck at VCC or GND
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rpirena.map.rpt: Warning (13410): Pin "RxD" is stuck at VCC
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rpirena.map.rpt: Warning (13410): Pin "LTxP[2]" is stuck at GND
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rpirena.map.rpt: Warning (13410): Pin "LTxP[1]" is stuck at GND
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rpirena.map.rpt: Warning (13410): Pin "LTxN[2]" is stuck at GND
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rpirena.map.rpt: Warning (13410): Pin "LTxN[1]" is stuck at GND
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rpirena.map.rpt:Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
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rpirena.map.rpt:Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
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rpirena.map.rpt:Warning: Design contains 17 input pin(s) that do not drive logic
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rpirena.map.rpt: Warning (15610): No output dependent on input pin "spi_cs[1]"
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rpirena.map.rpt: Warning (15610): No output dependent on input pin "TxD"
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rpirena.map.rpt: Warning (15610): No output dependent on input pin "LRx[2]"
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rpirena.map.rpt: Warning (15610): No output dependent on input pin "LRx[1]"
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rpirena.map.rpt: Warning (15610): No output dependent on input pin "LRTx[2]"
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rpirena.map.rpt: Warning (15610): No output dependent on input pin "LRTx[1]"
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rpirena.map.rpt: Warning (15610): No output dependent on input pin "EE[0]"
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rpirena.map.rpt: Warning (15610): No output dependent on input pin "EE[1]"
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rpirena.map.rpt: Warning (15610): No output dependent on input pin "EE[2]"
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rpirena.map.rpt: Warning (15610): No output dependent on input pin "EE[3]"
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rpirena.map.rpt: Warning (15610): No output dependent on input pin "EE[4]"
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rpirena.map.rpt: Warning (15610): No output dependent on input pin "EE[5]"
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rpirena.map.rpt: Warning (15610): No output dependent on input pin "EE[6]"
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rpirena.map.rpt: Warning (15610): No output dependent on input pin "EE[7]"
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rpirena.map.rpt: Warning (15610): No output dependent on input pin "EE[8]"
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rpirena.map.rpt: Warning (15610): No output dependent on input pin "EE[9]"
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rpirena.map.rpt: Warning (15610): No output dependent on input pin "EE[10]"
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rpirena.map.rpt:Info: Quartus II Analysis & Synthesis was successful. 0 errors, 109 warnings
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rpirena.sta.rpt:Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings
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