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solo_altera/stein/altera/3385.patch.annotated
stephan 0e5c2920c7 stein: annotated patch for -c 3385 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3386 bc5caf13-1734-44f8-af43-603852e9ee25
2014-10-26 09:50:12 +00:00

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> Index: stein/altera/stein_frontend.v
> ===================================================================
> --- stein/altera/stein_frontend.v (revision 3384)
> +++ stein/altera/stein_frontend.v (revision 3385)
> @@ -26,7 +26,7 @@
> input [2:0] acq_time1,
> input [2:0] acq_time2,
> input [1:2] all,
>AAA - input [18:0] timestamp,
>AAA + input [31:0] timestamp,
AAA: The ARxSTREAM supports 32 bit timestamps, the backend provides 24 bits, we could add 8 bits from the seconds clock.
> output [1:0] l2cls1,
> output [1:0] l2cls2,
> output [1:2] e_start,
> @@ -49,6 +49,8 @@
> input [1:0] thbp2,
> input [5:0] thsum1,
> input [5:0] thsum2,
>BBB + input [7:0] th_dtime1,
>BBB + input [7:0] th_dtime2,
BBB: The L2 trigger rejects events based on minimum dtime
>
> input [1:2] TRIG,
> input [1:2] DOUT,
> @@ -57,7 +59,7 @@
> output [1:2] DIN,
> output [5:0] DEBUG,
>
>CCC - output [1:2] hss
>CCC + output hss
CCC: The ARxSTREAMs are merged into one serializer.
> );
>
> wire [1:0] ix_adc_req;
> @@ -69,6 +71,9 @@
> .adc_valid(adc_valid), .adc_channel(adc_channel), .adc_sampled(adc_sampled),
> .adc_d1(adc_d1), .adc_d2(adc_d2), .adc_chn(adc_chn)
> );
>CCC +
>CCC + wire [1:2] stream_ack, stream_en;
> + wire [15:0] stream_data[1:2];
>
> stein_ix_controller #(.MODULE_NR(0)) ix_controller1
> (
> @@ -77,13 +82,13 @@
> .all(all[1]), .timestamp(timestamp),
> .l2cls(l2cls1), .e_start(e_start[1]), .e_next(e_next[1]), .e_done(e_done[1]), .data(data1),
> .baseline(baseline1),
>BBB - .thsp(thsp1), .thlp(thlp1), .thbp(thbp1), .thsum(thsum1),
>BBB + .thsp(thsp1), .thlp(thlp1), .thbp(thbp1), .thsum(thsum1), .th_dtime(th_dtime2),
> .TRIG(TRIG[1]), .DOUT(DOUT[1]), .STROBE(STROBE[1]), .RD(RD[1]), .DIN(DIN[1]),
> .adc_sampled(adc_sampled), .adc_valid(adc_valid), .adc_channel(adc_channel),
> .adc_d1(adc_d1), .adc_d2(adc_d2),
> .adc_chn(adc_chn), .adc_request(ix_adc_req[0]),
> .token(token1), .ack(ack[1]), .nack(nack[1]), .fifo_full(1'b0),
>CCC - .hss(hss[1]),
>CCC + .stream_en(stream_en[1]), .stream_ack(stream_ack[1]), .stream(stream_data[1]),
> .DEBUG(DEBUG)
> );
>
> @@ -94,16 +99,34 @@
> .all(all[2]), .timestamp(timestamp),
> .l2cls(l2cls2), .e_start(e_start[2]), .e_next(e_next[2]), .e_done(e_done[2]), .data(data2),
> .baseline(baseline2),
>BBB - .thsp(thsp2), .thlp(thlp2), .thbp(thbp2), .thsum(thsum2),
>BBB + .thsp(thsp2), .thlp(thlp2), .thbp(thbp2), .thsum(thsum2), .th_dtime(th_dtime2),
> .TRIG(TRIG[2]), .DOUT(DOUT[2]), .STROBE(STROBE[2]), .RD(RD[2]), .DIN(DIN[2]),
> .adc_sampled(adc_sampled), .adc_valid(adc_valid), .adc_channel(adc_channel),
> .adc_d1(adc_d1), .adc_d2(adc_d2),
> .adc_chn(adc_chn), .adc_request(ix_adc_req[1]),
> .token(token2), .ack(ack[2]), .nack(nack[2]), .fifo_full(1'b0),
>CCC - .hss(hss[2]),
>CCC + .stream_en(stream_en[2]), .stream_ack(stream_ack[2]), .stream(stream_data[2]),
> .DEBUG()
> );
>CCC +
>CCC +`ifdef ARxSTREAM
>CCC +
>CCC + wire s_en = |stream_en;
>CCC + wire s_ack;
>CCC + wire s_data = s_en[1] ? stream_data[1] : stream_data[2];
>CCC + assign stream_ack[1] = s_ack;
>CCC + assign stream_ack[2] = s_ack & ~stream_en[1];
>CCC
>CCC + serialize serializer
>CCC + (
>CCC + .mclk(clk),
>CCC + .data_e(s_en), .data_ack(s_ack), .data(s_data),
>CCC + .cntr_e(1'b0), .cntr_ack(), .cntr(16'b0),
>CCC + .sclk(clk), .out(hss)
>CCC + );
>CCC +
>CCC +`endif
>CCC +
> endmodule // stein_frontend
>
> `ifdef STEIN_FRONTEND_TEST
> Index: stein/altera/stein.v
> ===================================================================
> --- stein/altera/stein.v (revision 3384)
> +++ stein/altera/stein.v (revision 3385)
> @@ -63,14 +63,11 @@
> .locked(locked)
> );
>
>DDD - reg [1:2] DOUTT, TRIGG;
>DDD + reg [1:2] DOUTT, DOUTM, TRIGG;
DDD: re-register DOUT on @(negedge xclk) before feeding into 24MHz logic
DDD: _ _ _ _ _ _ _
DDD: xclk _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
DDD: ___ ___ ___ ___
DDD: mclk __/ \___/ \___/ \___/
DDD: _____ ___________ ___________
DDD: DOUTT _____X___________X___________
DDD: __________ __________ _______
DDD: DOUTM __________X__________X_______
DDD: __________________ _______ __
DDD: dout __________________X_______X__
> always @(posedge xclk)
> begin
> DOUTT <= DOUT;
> TRIGG <= TRIG;
>DDD - end
>DDD - always @(posedge xclk)
>DDD - begin
> DIN <= DDIN;
> STROBEp <= SSTROBEp;
> STROBEn <= SSTROBEn;
> @@ -78,7 +75,10 @@
> READ <= RREAD;
> TEST <= TTEST;
> end
>DDD -
>DDD + end
>DDD + always @(negedge xclk)
>DDD + DOUTTM <= DOUTT;
>DDD +
> `ifdef M24MHZ
> reg clk;
> always @(posedge xclk)
> @@ -114,7 +114,7 @@
> .mgo(sram_go),.mwrite(sram_write), .eeprom(eeprom),
> .maddr(sram_addr), .mdata(sram_data), .qm(sram_q),
> .TRIG(trig), .TEST(TTEST),
>DDD - .STROBE(SSTROBEp), .RD(RREAD), .SC(SSC), .DIN(DDIN), .DOUT(DOUTT),
>DDD + .STROBE(SSTROBEp), .RD(RREAD), .SC(SSC), .DIN(DDIN), .DOUT(DOUTT), .DOUTM(DOUTM),
> .ADC_CS(ADC_CSp[1]), .ADC_SCLK(ADC_SCLKp[1]), .ADC_DIN(ADC_DIN[1]),
> .ADC_DOUT(ADC_DOUT[1:2]),
> .OH_pwm(LVPS_PWM_OP_HEATER),
> Index: stein/altera/stein_ix_controller.v
> ===================================================================
> --- stein/altera/stein_ix_controller.v (revision 3384)
> +++ stein/altera/stein_ix_controller.v (revision 3385)
> @@ -8,7 +8,11 @@
> // STROBE vs DOUT timing.
>
> module stein_ix_controller
>EEE - #(parameter MODULE_NR=0, MCLK=48)
>EEE + #(parameter
>EEE + MODULE_NR = 0,
>EEE + MCLK = 48,
>EEE + DOUT_DELAY = 2,
>EEE + AOUT_DELAY = 1 )
EEE: Two parameters describe the delay incured by the IO-pad registers
EEE: for the Idef-X controlls.
EEE: DOUT_DELAY=2: two xclk cycles added STROBE --> DOUT.
EEE: AOUT_DELAY=1: one clock cycle added STROBE --> AOUT (unused).
EEE: The AOUT delay cannot easily be accommodated, it cuts
EEE: into the settling time.
> (
> input clk,
> input reset,
> @@ -18,7 +22,7 @@
> input [7:0] read_delay,
> input [2:0] acq_time,
> input all,
>AAA - input [18:0] timestamp,
>AAA + input [31:0] timestamp,
> output [1:0] l2cls,
> output e_start,
> output e_next,
> @@ -31,7 +35,8 @@
> input [3:0] thlp,
> input [1:0] thbp,
> input [5:0] thsum,
>BBB -
>BBB + input [7:0] th_dtime,
>BBB +
> // IDEF-X
> input TRIG,
> input DOUT,
> @@ -50,23 +55,20 @@
>
> // MIDDLEEND
> input fifo_full,
>FFF - output reg [31:0] token,
>FFF + output [31:0] token,
FFF: Move the saved token register into the ix_acquire module.
> output ack,
> output nack,
>
> // Highspeed streaming
>AAA - output hss,
>AAA + output stream_en,
>AAA + input stream_ack,
>AAA + output [15:0] stream_data,
>
> output [5:0] DEBUG
> );
>
>AAA - wire stream_en, stream_ack, cntr_ack;
>AAA -
> wire ack1, nack1, tokene;
>FFF - wire [31:0] tokens;
>FFF - always @(posedge clk)
>FFF - if (tokene)
>FFF - token <= tokens;
>BBB + wire [7:0] dtime;
>
> assign ack = ack1 & ~fifo_full;
> assign nack = nack1 | ack1 & fifo_full;
> @@ -73,11 +75,12 @@
> wire [4:0] l2trig_sum;
> wire [3:0] l2lp, l2sp;
> wire [1:0] l2bp;
>CCC - wire [15:0] stream_data, cntr_data;
CCC: The ARxSTREAM control channel is unused
> wire [18:0] acq_data;
> assign data = {30'b0, l2sp, l2lp, l2bp, l2trig_sum, acq_data};
>
>EEE - stein_ix_acquire #(.MODULE_NR(MODULE_NR), .MCLK(MCLK)) ix_acquire
>EEE + stein_ix_acquire
>EEE + #(.MODULE_NR(MODULE_NR), .MCLK(MCLK), .DOUT_DELAY(DOUT_DELAY), .AOUT_DELAY(AOUT_DELAY))
>EEE + ix_acquire
> (.clk(clk), .enable(enable_acquire),
> .DOUT(DOUT), .TRIG(TRIG), .STROBE(STROBE), .RD(RD), .DIN(DIN),
> .adc_data_valid(adc_valid), .adc_sampled(adc_sampled), .adc_data1(adc_d1), .adc_data2(adc_d2),
> @@ -84,8 +87,9 @@
> .adc_channel(adc_channel), .adc_req(adc_request),
> .baseline(baseline),
> .read_delay(read_delay), .acq_time(acq_time), .all(all),
>BBB - .ack(ack1), .nack(nack1), .tokens(tokens), .tokene(tokene),
>BBB + .ack(ack1), .nack(nack1), .token(token), .tokene(tokene), .dtime(dtime),
> .e_start(e_start), .e_next(e_next), .e_done(e_done), .data(acq_data),
>AAA + .clock(timestamp),
> .stream_en(stream_en), .stream_ack(stream_ack), .stream(stream_data),
> .acq_debug(DEBUG));
>
> @@ -92,8 +96,8 @@
> stein_l2trig l2trig
> (
> .clk(clk),
>BBB - .tokene(tokene), .tokens(tokens),
>BBB - .thsp(thsp), .thlp(thlp), .thbp(thbp), .thsum(thsum),
>BBB + .tokene(tokene), .tokens(token), .dtime(dtime),
>BBB + .thsp(thsp), .thlp(thlp), .thbp(thbp), .thsum(thsum), .th_dtime(th_dtime),
> .sp(l2sp), .lp(l2lp), .bp(l2bp), .sum(l2trig_sum),
> .ack(ack1), .nack(nack1)
> );
> @@ -105,23 +109,6 @@
> .cls(l2cls)
> );
>
>CCC - reg cntr_en;
>CCC - always @(posedge clk)
>CCC - if(reset | cntr_ack)
>CCC - cntr_en <= 0;
>CCC - else if(ack1)
>CCC - cntr_en <= 1;
>CCC -
>CCC - assign cntr_data = {1'b0, l2sp, l2lp, l2bp, l2trig_sum};
>CCC -
>CCC - serialize serializer
>CCC - (
>CCC - .mclk(clk),
>CCC - .data_e(stream_en), .data_ack(stream_ack), .data(stream_data),
>CCC - .cntr_e(cntr_en), .cntr_ack(cntr_ack), .cntr(cntr_data),
>CCC - .sclk(clk), .out(hss)
>CCC - );
>CCC -
> endmodule // stein_ix
>
> module stein_ix_reset
> @@ -457,41 +444,36 @@
> `endif // `ifdef IX_TEMP_TEST
>
> module stein_ix_slow_control
>EEE - #(parameter MCLK=48)
>EEE + #(parameter MCLK=48, FO=2, DOUT_DELAY=0)
> (
> - input clk,
> + input clk,
>
> - input we,
> - input wa,
> - input [63:0] wd,
> - input [6:0] addr,
> - input [7:0] len,
> - input rw,
> - output busy,
> - output re,
> - output [63:0] rd,
> -
>GGG - output reg STROBE,
>GGG - output reg SC,
>GGG - output reg DIN,
>GGG - input DOUT
> + input we,
> + input wa,
> + input [63:0] wd,
> + input [6:0] addr,
> + input [7:0] len,
> + input rw,
>HHH + output reg busy,
> + output re,
> + output [63:0] rd,
> +
>GGG + input [1:FO] sel,
>GGG + output reg [1:FO] STROBE,
>GGG + output reg [1:FO] SC,
>GGG + output reg [1:FO] DIN,
>GGG + input [1:FO] DOUT
GGG: Move the slow control IDEF-X selection into ix_slow_control
GGG: to register the outputs for precise transition into 48MHz.
> );
>
> parameter CLK_DIV = MCLK/12-1;
> parameter NB_CLK_DIV = 3;
>
>HHH - reg nn;
>HHH - assign busy = nn;
HHH: rename stein_ix_slow_control.nn to busy
> -
> - wire start;
>HHH - assign start = we & ~wa;
>HHH + wire start = we & ~wa;
HHH: combine wire decl.and assign into one statement.
>
>HHH - reg [191:0] dsr; // data shift register
>HHH - reg [7:0] asr; // address shift register
> reg [7:0] n;
>
> always @(posedge clk)
>HHH - nn <= |n | start;
>HHH + busy <= |n | start;
>
> reg [NB_CLK_DIV:1] cdiv;
> wire tick = ~|cdiv;
> @@ -501,7 +483,7 @@
> cdiv <= 0;
> else if (~tick)
> cdiv <= cdiv - 1;
>HHH - else if (nn)
>HHH + else if (busy)
> cdiv <= CLK_DIV;
>
> `ifdef SIMULATION
> @@ -510,26 +492,29 @@
> cdiv <= 0;
> end
> `endif
> -
> +
>GGG + reg strobe;
>GGG always @(posedge clk)
>GGG if (we)
>GGG - STROBE <= 0;
>GGG + {STROBE,strobe} <= 0;
>GGG else if (tick)
>GGG - if (STROBE)
>GGG - STROBE <= 0;
>GGG + if (strobe)
>GGG + {STROBE,strobe} <= 0;
>GGG + else if (busy)
>GGG + {STROBE,strobe} <= {sel,1'b1};
>GGG else
>GGG - STROBE <= nn;
>GGG + {STROBE,strobe} <= 0;
>
> always @(posedge clk)
> if (we & wa)
> SC <= 0;
>GGG - else if (tick & ~STROBE)
>GGG - SC <= n>4;
>GGG + else if (tick & ~strobe & n>4)
>GGG + SC <= sel;
>
> always @(posedge clk)
> if (start)
> n <= len + 12;
>GGG - else if (tick & STROBE)
>GGG + else if (tick & strobe)
> n <= n - 1;
>
> reg [7:0] l;
> @@ -543,38 +528,61 @@
> n <= 0;
> end
> `endif
> -
>III - always @(posedge clk)
>III - if(we)
>III - DIN <= 0;
>III - else if (tick & ~STROBE)
>III - if(n > (l+4))
>III - DIN <= asr[7];
>III - else if(n>4)
>III - DIN <= dsr[191];
>III - else
>III - DIN <= 0;
>
>EEE - reg z;
>EEE + // Sample DOUT just before negedge STROBE. Take DOUT_DELAY clk
>EEE + // cycles delay into account. With additional registers in STROBE
>EEE + // and DOUT in the IO pads, the DOUT_DELAY is 2 clk cycles.
>EEE + // 'dout_tick' and the else clause will optimize out for
>EEE + // DOUT_DELAY==0.
>EEE + reg [0:DOUT_DELAY] dout_tick;
>EEE + reg [1:FO] dout;
>EEE always @(posedge clk)
>EEE - if(start)
>EEE - z <= rw;
>EEE -
>EEE - always @(posedge clk)
>EEE - if(tick & STROBE & nn & (n < (l+5-z)) & (n>4-z))
>EEE - dsr <= {dsr[190:0], DOUT};
>EEE - else if (wa)
>EEE - dsr <= {wd, dsr[191:64]};
>EEE + if (tick & strobe)
>EEE + begin
>EEE + dout <= DOUT;
>EEE + dout_tick <= (1<<DOUT_DELAY)-1;
>EEE + end
>EEE + else if (dout_tick[DOUT_DELAY])
>EEE + begin
>EEE + dout <= DOUT;
>EEE + dout_tick <= dout_tick>>1;
>EEE + end
>
>III + // Shift DIN at posedge STROBE.
>III + reg shift_data, shift_addr;
>III + reg [191:0] dsr;
>III + reg [6:0] asr;
>III always @(posedge clk)
>III - if(start) // !!!
>III - asr <= {rw, addr};
>III - else if(tick & STROBE & nn)
>III - asr <= {asr[6:0], 1'b0};
>III + begin
>III + shift_addr <= n > l+4;
>III + if (tick&strobe)
>III + shift_data <= 4 < n;
>III +
>III + if (wa)
>III + dsr <= {wd, dsr[191:64]};
>III + else if (we)
>III + begin
>III + asr <= addr;
>III + DIN <= sel & {FO{ rw }};
>III + end
>III + else if (tick & ~strobe)
>III + if (shift_addr)
>III + begin
>III + asr[6:1] <= asr[5:0];
>III + DIN <= sel & {FO{ asr[6] }};
>III + end
>III + else if (shift_out)
>III + begin
>III + dsr <= {dsr[190:0],|(dout&sel)};
>III + DIN <= sel & {FO{ dsr[190] }};
>III + end
>III + else
>III + DIN <= 0;
>III + end
III: Rework of the SC shift regsiters, to accomodate EEE.
>
> assign re = wa;
> assign rd = dsr[63:0];
> -
> +
> endmodule // stein_ix_slow_control
>
> // 0: 0 test
> @@ -587,6 +595,7 @@
> // 7: - temp readout
>
> module stein_ix_sc_scheduler
>EEE + #(parameter DOUT_DELAY=0)
> (
> input clk,
>
> @@ -663,23 +672,13 @@
> reg [2:0] start_read;
> reg [6:0] ra;
> reg [7:0] length;
>EEE - stein_ix_slow_control ix_slow_control
>EEE + stein_ix_slow_control #(.FO(2), .DOUT_DELAY(DOUT_DELAY)) ix_slow_control
> (.clk(clk),
> .we(go|ld|start_read[2]), .wa(ld|wa), .wd(wd), .addr(addr|ra), .len(len|length), .rw(start_read[2]),
> .busy(sc_busy), .re(re), .rd(rd),
>GGG - .STROBE(strobe), .SC(sc), .DIN(din), .DOUT(dout)
>GGG + .sel(port_mask), .STROBE(STROBE), .SC(SC), .DIN(DIN), .DOUT(DOUT)
> );
>
>GGG - always @(posedge clk)
>GGG - begin
>GGG - STROBE <= {2{strobe}} & port_mask;
>GGG - SC <= {2{sc}} & port_mask;
>GGG - DIN <= {2{din}} & port_mask;
>GGG - end
>GGG -
>GGG - always @(posedge clk)
>GGG - dout <= |(DOUT & read_mask);
>GGG -
> reg pending;
> always @(posedge clk)
> pending <= reqq == busy;
> @@ -912,7 +911,9 @@
> module stein_ix_acquire
> #(parameter
> MODULE_NR=1'b0, //MODULE_NR may be 1'b0 or 1'b1
>EEE - MCLK=48 )
>EEE + MCLK=48,
>EEE + DOUT_DELAY=2, // Delay from negedge STROBE to DOUT due to IOpad regsiters.
>EEE + AOUT_DELAY=1 ) // Delay from STROBE to AOUT due to IOpad regsiter.
> (
> input clk,
> input enable, // enable triggers
> @@ -919,7 +920,7 @@
>
> input DOUT,
> input TRIG,
> - output STROBE,
>EEE + output reg STROBE,
> output reg RD,
> output reg DIN,
>
> @@ -937,23 +938,28 @@
>
> input ack, // L2 trigger: digitize
> input nack, // L2 trigger: no not digitize
>FFF - output reg [31:0] tokens, // trigger tokens
>FFF + output reg [31:0] token, // trigger tokens
> output tokene, // trigger tokens are valid,
>BBB + output reg [7:0] dtime,
>
> output reg e_start, // tell the backend new message is starting
> output reg e_next, // tell it next dataword is coming
> output reg e_done, // tell it message is complete
>HHH - output [18:0] data, //contains L3 and PHA data, each 32 bit
>HHH + output [18:0] data,
HHH: Removed wrong comment
>
>AAA + input [31:0] clock,
>AAA +
> output reg stream_en,
> input stream_ack,
>CCC - output [15:0] stream,
>CCC + output reg [15:0] stream,
> +
>HHH + output reg timeouts, // feed this into a counter
HHH: timeouts shall be counted
> output [5:0] acq_debug
> );
>
> assign acq_debug[5:0] = 0;
>
>JJJ - wire start;
>JJJ + wire start, trig;
JJJ: The input to the timeout counter is extraced from the debouncer.
> debounce dbnc
> (.clk(clk),
> .sync(1'b1),
> @@ -962,144 +968,180 @@
> .enable(enable),
> .extrig(1'b0),
> .delay(read_delay),
>JJJ - .tout(start) );
>JJJ + .tout(start),
>JJJ + .tinn(trig) );
>
> - wire adc_v, adc_s;
> - reg [2:0] acq_wait;
> + reg reset;
> +
> + reg [5:0] n; // 32 Strobes to check which pixel got hit
> + reg [5:0] m; // count how many pixel got hit
> + reg mm, nn, mm1, nn1, nnn, eon, eom;
> +
> reg wait_adcv;
> - reg mm;
> - assign adc_v = adc_data_valid & (adc_channel==MODULE_NR) & wait_adcv;
> - assign adc_s = adc_sampled & (adc_channel==MODULE_NR) & mm & ~|acq_wait;
> -
> - wire reset = ~enable | timeout;
> + wire acq_settled;
> + wire adc_v = adc_data_valid & (adc_channel==MODULE_NR) & wait_adcv;
> + wire adc_s = adc_sampled & (adc_channel==MODULE_NR) & acq_settled;
> + always @(posedge clk)
> + if (reset | adc_v)
> + wait_adcv <= 0;
> + else if (adc_s)
> + wait_adcv <= 1;
>
> reg [1:0] cdiv;
> wire tick = ~|cdiv;
> always @(posedge clk)
> - if(tick)
> + if (start | tick | adc_s)
> cdiv <= MCLK/24 - 1;
> - else if(~tick)
> + else
> cdiv <= cdiv - 1;
>
> - reg [6:0] musec; // mu second counter
> - reg strobe;
> - reg [5:0] n; // 32 Strobes to check which pixel got hit
> always @(posedge clk)
> - if(~|musec | strobe & tick & n==1)
> - musec <= MCLK-1;
> - else
> - musec <= musec - 1;
> + RD <= mm | timeout;
>
> - reg mutick; //one tick every mu second
> always @(posedge clk)
> - mutick <= ~|musec;
>KKK + if (start | reset)
>KKK + STROBE <= 0;
>KKK + else if (mm1 & adc_s)
>KKK + STROBE <= 1;
>KKK + else if (tick)
>KKK + if (STROBE)
>KKK + STROBE <= 0;
>KKK + else if (nn)
>KKK + STROBE <= 1;
>KKK +
>KKK + always @(posedge clk)
>KKK + DIN = nn & all;
KKK: Rework of the ix_acquire state machine.
> +
>EEE + // Sample DOUT just before negedge STROBE. Take DOUT_DELAY clk
>EEE + // cycles delay into account. With one additional register each in
>EEE + // STROBE and DOUT in the IO pads, the DOUT_DELAY is 2 clk cycles.
>EEE + //
>EEE + // The last token must be read without a STROBE.
>EEE + reg [0:DOUT_DELAY] dout_tick;
>EEE + wire dtick = dout_tick[DOUT_DELAY];
>EEE + reg tdelay;
>EEE + reg [1:0] dout_pipe;
>EEE + reg dout;
>EEE
>EEE always @(posedge clk)
>KKK - if(strobe)
>KKK - acq_wait <= acq_time;
>KKK - else if(mutick & |acq_wait)
>KKK - acq_wait <= acq_wait - 1;
>KKK -
>KKK - // In Sim cdiv (tick), musec, mutick and acq_wait are 'X', but in hardware they work like intended (formulation of else clauses)
>HHH -`ifdef SIMULATION
>HHH - initial
>HHH begin
>HHH - cdiv <= 0;
>HHH - musec <= 0;
>HHH - acq_wait <= 0;
HHH: Move all SIMULATION code to the end of the module
>EEE + tdelay <= |{dout_tick,dout_pipe};
>EEE + if (tick)
>EEE + dout_pipe <= {dout_pipe[0], STROBE & nn};
>EEE + if (tick & dout_pipe[1])
>EEE + begin
>EEE + dout <= DOUT;
>EEE + dout_tick <= 1<<DOUT_DELAY;
>EEE + end
>EEE + else
>EEE + begin
>EEE + if (|(dout_tick>>1))
>EEE + dout <= DOUT;
>EEE + dout_tick <= dout_tick>>1;
>EEE + end
> end
>HHH -`endif
>KKK -
>KKK - reg nn;
>KKK - reg lastn;
>KKK - always @(posedge clk)
>KKK - RD <= |{nn, mm, lastn, timeout};
>
>KKK - reg got_adcs;
>KKK - reg [5:0] m; // count how many pixel got hit
>KKK - always @(posedge clk)
>KKK - if(start|reset)
>KKK - strobe <= 0;
>KKK - else if(tick)
>KKK - if(strobe)
>KKK - strobe <= 0;
>KKK - else if(m>1 | nn)
>KKK - strobe <= nn | got_adcs;
>KKK + reg [4:0] chn_nr;
>KKK
>KKK - assign STROBE = strobe;
>KKK -
>KKK - reg [1:0] strobee;
>KKK - always @(posedge clk)
>KKK - if(tick)
>KKK - strobee <= {strobee[0], strobe};
>KKK + // This is the state machine, state n,m.
>KKK + // n: number of tokens to read
>KKK + // m: number of values to digitize
>KKK + // nn==n>0 nn1==n>1
>KKK + // mm==m>0 mm1==m>1
>KKK + // nnn: include time to wait for the last tokens after nn
>KKK + // eon: token shift completed now, (m,tokens) is valid
>KKK + // eom: digitization finished now.
>KKK
>KKK - always @(posedge clk)
>KKK - DIN <= nn & all;
>KKK + reg [31:0] tokens;
>KKK + assign tokene = eon;
>KKK
>KKK always @(posedge clk)
>KKK - if(reset)
>KKK - n <= 0;
>KKK - else if(start)
>KKK - n <= 32;
>KKK - else if(tick & strobe & nn)
>KKK - n <= n - 1;
>KKK + begin
>KKK + if (nnn & tick)
>KKK + token <= tokens;
>KKK
>KKK - always @(posedge clk)
>KKK - nn <= |n;
>KKK + nn <= |n;
>KKK + nn1 <= n>1;
>KKK + nnn <= |n | tdelay;
>KKK + eon <= nnn & ~nn & ~tdelay;
>KKK +
>KKK + mm <= |m;
>KKK + mm1 <= m>1;
>KKK + eom <= mm & ~|m;
>KKK
>KKK - always @(posedge clk)
>KKK - if(nn)
>KKK - lastn <= 1;
>KKK - else if(tick & ~|strobee)
>KKK - lastn <= 0;
>KKK + if (reset|nack)
>KKK + begin
>KKK + n <= 0;
>KKK + m <= 0;
>KKK + end
>KKK + else if (start)
>KKK + begin
>KKK + n <= 32;
>KKK + m <= 1;
>KKK + end
>KKK + else if (tick & nn & STROBE)
>KKK + n = n-1;
>KKK + else if (dtick)
>KKK + begin
>KKK + tokens <= {dout, tokens[31:1]};
>KKK + if (all)
>KKK + m <= 33;
>KKK + else if (dout)
>KKK + m <= m+1;
>KKK + end
>KKK + else
>KKK + begin
>KKK + if(eon)
>KKK + chn_nr <= 0;
>KKK + else if(~nnn & mm & (~tokens[0] & ~all | e_next))
>KKK + begin
>KKK + chn_nr <= chn_nr + 1;
>KKK + tokens <= tokens >> 1;
>KKK + end
>KKK +
>KKK + if(~nn & adc_v)
>KKK + m <= m - 1;
>KKK + end
>KKK + end
>KKK
>KKK - reg eon; // end of n
>KKK - always @(posedge clk)
>KKK - eon <= lastn & tick & ~|strobee & ~nn;
>KKK + // Define the ADC driver settling time: (acq_time+1) µs
>KKK + // After that time, the next digitization that comes
>KKK + // along will be used.
>KKK
>KKK + reg [6:0] musec;
>KKK always @(posedge clk)
>KKK - if(reset|start|nack)
>KKK - m <= 0;
>KKK - else if(eon & mm)
>KKK - m <= m + 1; //add one for the baseline
>KKK - else if(nn & all)
>KKK - m <= 32;
>KKK - else if(lastn & tick & strobee[1] & DOUT)
>KKK - m <= m + 1;
>KKK - else if(~nn & adc_v)
>KKK - m <= m - 1;
>KKK -
>KKK - always @(posedge clk)
>KKK - mm <= |m;
>KKK + if (~|musec | nn1)
>KKK + musec <= MCLK-1;
>KKK + else
>KKK + musec <= musec - 1;
>KKK
>KKK - reg eom;
>KKK + reg mutick;
>KKK always @(posedge clk)
>KKK - eom <= mm & ~|m;
>KKK + mutick <= ~|musec;
>KKK
>KKK - assign tokene = eon;
>KKK -
>KKK - always @(posedge clk)
>KKK - if(lastn & tick & strobee[1])
>KKK - tokens <= {DOUT, tokens[31:1]};
>KKK - else if(~lastn & ~eon & mm & (~tokens[0] | e_next)) // channel_nr
>KKK - tokens <= tokens >> 1;
>KKK + reg [3:0] acq_wait;
>KKK + assign acq_settled = mm & acq_wait[3];
>KKK
>KKK always @(posedge clk)
>KKK - adc_req <= n<27 & (lastn | mm | wait_adcv);
>KKK + if (STROBE)
>KKK + acq_wait <= {1'b0,acq_time};
>KKK + else if (mutick & ~acq_settled)
>KKK + acq_wait <= acq_wait - 1;
>KKK
>KKK always @(posedge clk)
>KKK - if(adc_s)
>KKK - got_adcs <= 1;
>KKK - else if(reset|strobe|adc_v)
>KKK - got_adcs <= 0;
> -
>BBB + if (reset | eom)
>BBB + dtime <= 0;
>BBB + else if (mutick & ~&dtime)
>BBB + dtime <= dtime + 1;
> +
>KKK + // The adc request is asserted such that the baseline settling time is
>KKK + // just about as requested, when the ADC was idle.
>KKK always @(posedge clk)
>KKK - if(reset|adc_v)
>KKK - wait_adcv <= 0;
>KKK - else if(adc_s)
>KKK - wait_adcv <= 1;
>KKK + adc_req <= n<27 & (nnn | mm | wait_adcv);
>
>HHH - reg bldig; // baseline digitizing
>HHH + // Digitization
>HHH +
>HHH + reg bldig;
> always @(posedge clk)
> if(reset|adc_v)
> bldig <= 0;
> @@ -1107,6 +1149,7 @@
> bldig <= 1;
>
> wire [12:0] adc_diff = {1'b0, adc_data2} - {1'b0, adc_data1};
> +
> always @(posedge clk)
> if(adc_v & bldig)
> baseline <= adc_diff;
> @@ -1114,6 +1157,8 @@
> reg [13:0] adc_data;
> always @(posedge clk)
> adc_data <= {adc_diff[12], adc_diff} - {baseline[12], baseline};
> +
> + // Event formatting.
>
> always @(posedge clk)
> e_start <= ack;
> @@ -1123,7 +1168,7 @@
>
> reg ackk;
> always @(posedge clk)
>KKK - if(reset | eom)
>KKK + if(nack)
> ackk <= 0;
> else if(ack)
> ackk <= 1;
KKK: This was evil: The nack case was inherrited from the distand past.
KKK: eom was not even guarateed to happen.
> @@ -1131,20 +1176,38 @@
> always @(posedge clk)
> e_done <= eom & ackk;
>
>CCC - reg toggle_d;
>KKK + reg [4:0] channel_nr;
> always @(posedge clk)
> if(adc_v)
>CCC - toggle_d <= 0;
>CCC - else if(stream_ack)
>CCC - toggle_d <= ~toggle_d;
>KKK + channel_nr <= chn_nr;
>KKK + assign data = {channel_nr, adc_data};
> +
> + // TIMEOUT, in case the trigger is stuck, send an analog reset.
>
> + reg [5:0] timeout_counter;
> + reg [2:0] timeout_len;
> + reg timeout;
> +
> always @(posedge clk)
>CCC - if(reset | stream_ack)
>CCC - stream_en <= 0;
>CCC - else if(adc_v | toggle_d)
>CCC - stream_en <= 1;
>KKK + begin
>KKK + reset <= ~enable | timeout;
>
>KKK + if (reset | ~trig | STROBE)
>KKK + timeout_counter <= 0;
>KKK + else if (mutick)
>KKK + timeout_counter <= timeout_counter + 1;
>KKK +
>KKK + if (&timeout_counter)
>KKK + timeout_len <= ~0;
>KKK + else if (mutick & timeout)
>KKK + timeout_len <= timeout_len - 1;
>KKK +
>HHH + timeout <= |timeout_len;
HHH: timeout must be registerd, because it feeds into a lot of complex
HHH: conditionals.
>HHH + timeouts <= mutick & timeout_len==1;
>KKK + end
>KKK +
>HHH `ifdef SIMULATION
>HHH +
>HHH always @(posedge clk)
>HHH begin
>HHH if(e_start)
>HHH @@ -1153,59 +1216,63 @@
>HHH if(bldig)
>HHH $display("BASELINE: adc_data1: %05d | adc_data2: %05d", adc_data1, adc_data2);
>HHH else if(e_next)
>HHH - $display("DATA - channel: %02d | adc_data1: %05d | adc_data2: %05d | diff: %05d", channel_nr, adc_data1, adc_data2, adc_data2-adc_data1);
>HHH + $display("DATA - channel: %02d | adc_data1: %05d | adc_data2: %05d | diff: %05d",
>HHH + channel_nr, adc_data1, adc_data2, adc_data2-adc_data1);
>HHH if(e_done)
>HHH $display("=========== Finishing Event");
>HHH end
>HHH +
>HHH + initial
>HHH + begin
>HHH + cdiv <= 0;
>HHH + musec <= 0;
>HHH + acq_wait <= 0;
>HHH + timeout_len <= 0;
>HHH + end
>HHH `endif
> -
>KKK - reg [4:0] chn_nr;
>KKK - always @(posedge clk)
>KKK - if(eon)
>KKK - chn_nr <= 0;
>KKK - else if(mm & (~tokens[0] | e_next) & ~all)
>KKK - chn_nr <= chn_nr + 1;
>KKK - else if(mm & all & e_next & ~bldig)
>KKK - chn_nr <= chn_nr + 1;
>
>KKK - reg [4:0] channel_nr;
>KKK - always @(posedge clk)
>KKK - if(adc_v)
>KKK - channel_nr <= chn_nr;
> -
>CCC - assign stream = toggle_d ? {channel_nr, adc_data2[11:1]} : {channel_nr, adc_data1[11:1]};
>CCC + // serial stream, for calibration campains.
>
>CCC - assign data = {channel_nr, adc_data};
>CCC +`ifdef ARxSTREAM
>
>KKK - // TIMEOUT
>KKK - reg [2:0] trigg;
>CCC + reg [1:0] stream_header;
>CCC + reg [31:16] stream_high;
>CCC + reg stream_adcv;
> always @(posedge clk)
>KKK - trigg <= {trigg[1:0], TRIG};
>KKK -
>KKK - reg [5:0] timeout_counter;
>KKK - always @(posedge clk)
>KKK - if(reset|~trigg[2]|STROBE)
>KKK - timeout_counter <= 0;
>KKK - else if(mutick)
>KKK - timeout_counter <= timeout_counter + 1;
>KKK -
>KKK -`ifdef SIMULATION
>KKK - initial
> begin
>KKK - timeout_len <= $random;
>KKK - end
>KKK -`endif
>KKK - // In Hardware timeout_len become 0 after max 2**len(timeout_len)*1/48e6Hz (else clause)
>CCC + stream_adcv <= adc_v;
>CCC + if (start)
>CCC + begin
>CCC + stream <= {3'b100, MODULE_NR[0], 12'hdef};
>CCC + stream_header <= 'b 11;
>CCC + stream_en <= 1;
>CCC + end
>CCC + else if (stream_header[1] & stream_ack)
>CCC + begin
>CCC + stream_header <= stream_header << 1;
>CCC + stream_en <= 1;
>CCC + stream_high <= clock[31:16];
>CCC + if (stream_header[0])
>CCC + stream <= clock[15:0];
>CCC + else
>CCC + stream <= stream_high;
>CCC + end
>CCC + else if (tokene)
>CCC + begin
>CCC + stream <= tokens[15:0];
>CCC + stream_high <= tokens[15:0];
>CCC + stream_header[1] <= 1;
>CCC + end
>CCC + else if (stream_adcv)
>CCC + begin
>CCC + stream <= {MODULE_NR[0], bldig, 1'b1, adc_diff};
>CCC + stream_en <= 1;
>CCC + end
>CCC + else if (stream_ack)
>CCC + stream_en <= 0;
>CCC + end
>
>KKK - reg [5:0] timeout_len;
>KKK - always @(posedge clk)
>KKK - if(&timeout_counter)
>KKK - timeout_len <= ~0;
>KKK - else if(|timeout_len)
>KKK - timeout_len <= timeout_len - 1;
>KKK -
>KKK - wire timeout;
>KKK - assign timeout = |timeout_len;
>CCC +`endif // `ifdef ARxSTREAM
>
> endmodule // stein_ix_acquire
>
> Index: stein/altera/stein_core.v
> ===================================================================
> --- stein/altera/stein_core.v (revision 3384)
> +++ stein/altera/stein_core.v (revision 3385)
> @@ -29,6 +29,7 @@
> output [1:2] SC,
> output [1:2] DIN,
> input [1:2] DOUT,
>DDD + input [1:2] DOUTM,
> output [1:2] TEST,
>
> // ADC
> @@ -80,11 +81,10 @@
> wire [1:2] Txx;
>
>CCC `ifdef ARxSTREAM
>CCC - wire [1:2] ARxQ;
>CCC + wire ARxQ;
>CCC // looks like Tx[1] is the redundant port
>CCC - assign Tx = {Txx[1] & ~confs[4] & ~confs[5] | |ARxQ, Txx[2]};
>CCC - sermerge ARxM(.E(confs[4]), .C(xclk), .I(hss[1]), .Q(ARxQ[1]));
>CCC - sermerge ARxM(.E(confs[5]), .C(xclk), .I(hss[2]), .Q(ARxQ[2]));
>CCC + assign Tx = {Txx[1] & ~confs[4] | ARxQ, Txx[2]};
>CCC + sermerge ARxM(.E(confs[4]), .C(xclk), .I(hss), .Q(ARxQ));
> `else
> assign Tx = Txx;
> `endif
> @@ -420,7 +420,7 @@
> .ix(sc_w_ix|ix_reset_ix), .ld(sc_w_ld|ix_reset_ld), .go({sc_w_go, ix_temp_req, ix_temp_req, ix_reset_go}),
> .addr(add), .len(sc_w_len), .wd(sc_w_wd|{48'b0, ix_reset_wd}),
> .temp_busy(temp_busy), .sc_regs(sc_data),
>DDD - .STROBE(strobem), .SC(SC), .DIN(dinm), .RD(rdm), .DOUT(DOUT),
>DDD + .STROBE(strobem), .SC(SC), .DIN(dinm), .RD(rdm), .DOUT(DOUTM),
> .clear({2{strobes[10]}}), .tokens1(tokens1), .tokens2(tokens2), .ack(ack24), .nack(nack24),
> .mrb_e(mrb_e), .mrb_a(mrb_a), .mrb_l(mrb_l), .mrb_w(mrb_w), .mrb_d(mrb_d),
> .error(), .single(),
> @@ -438,10 +438,10 @@
> wire [2:0] adc_chn, adc_channel;
> wire [11:0] adc_d1, adc_d2;
>
>AAA - wire [18:0] timestamp;
>AAA + wire [31:0] timestamp;
> wire acq_reset;
>
>CCC - wire [1:2] hss;
>CCC + wire hss;
>
> wire [5:0] debug_fe;
>
> @@ -470,6 +470,7 @@
> .thlp1(l2_config[7:4]), .thlp2(l2_config[23:20]),
> .thbp1(l2_config[9:8]), .thbp2(l2_config[25:24]),
> .thsum1(l2_config[15:10]), .thsum2(l2_config[31:26]),
>BBB + .th_dtime1(0), .th_dtime2(0),
> .TRIG(TRIG), .DOUT(DOUT), .STROBE(strobef), .RD(rdf), .DIN(dinf),
> .hss(hss),
> .DEBUG(debug_fe)
> @@ -497,12 +498,13 @@
> // CONTROL
> reg utickk;
> always @(posedge mclk) utickk <= utick;
>AAA - clk_domain_switch #(.W(19)) clk_domain_switch_timestamp
>AAA + clk_domain_switch #(.W(24)) clk_domain_switch_timestamp
>AAA (
>AAA - .iclk(mclk), .oclk(xclk), .ide(utickk), .din(usecond[18:0]),
>AAA - .ode(), .dout(timestamp)
>AAA + .iclk(mclk), .oclk(xclk), .ide(utickk), .din(usecond),
>AAA + .ode(), .dout(timestamp[23:0])
> );
> -
>AAA + assign timestamp[31:24] = 0;
> +
> clk_domain_switch #(.W(1)) clk_domain_switch_reset
> (
> .iclk(mclk), .oclk(xclk), .ide(strobes[4]), .din(1'b0),
> Index: stein/altera/stein_adc_controller.v
> ===================================================================
> --- stein/altera/stein_adc_controller.v (revision 3384)
> +++ stein/altera/stein_adc_controller.v (revision 3385)
> @@ -20,13 +20,11 @@
> output reg [11:0] adc_d1, //last digitized data by adc1
> output reg [11:0] adc_d2, //last digitized data by adc2
> output reg [2:0] adc_chn //the channelnr of the data in the buffers b1 and b2
>HHH + // TODO: what is b1 and b2? Please avoid comments!
> );
>
>HHH - wire mtick;
>HHH - wire doute;
>HHH - wire din1;
>HHH - wire dine;
>HHH - wire dout1;
>HHH + wire tick, mtick;
>HHH + wire dout1, doute, din1, dine;
>
> wire reset = ~|req;
>
> @@ -34,7 +32,7 @@
> //tick: 16 ticks per conversation, mtick: 1 mtick when conversation is done
> (
> .clk(clk), .reset(reset), .resync(0), .CS(ADC_CS), .CSn(ADC_CSn),
>LLL - .SCLK(ADC_SCLK), .SCLKn(ADC_SCLKn), .tick(), .mtick(mtick),
>LLL + .SCLK(ADC_SCLK), .SCLKn(ADC_SCLKn), .tick(tick), .mtick(mtick),
> .dout1(dout1), .doute(doute), .din1(din1), .dine(dine)
> );
>
> @@ -45,9 +43,22 @@
> priority_encode #(.N(3)) priority_encode(.i(bp), .q(na));
>
> reg [1:3] dv;
>LLL + always @(posedge clk)
>LLL + if(reset)
>LLL + dv <= 0;
>LLL + else if(mtick & doute)
>LLL + dv <= {1'b1, dv[1:2]};
>LLL
>LLL + // TODO: Review. This was one tick too early!
>LLL + // And it refered uncessearily to ADC_CS.
>LLL + // Please do not refer to ADC output signals.
>LLL + reg din2;
>LLL always @(posedge clk)
>LLL - adc_sampled <= din1 & (&dv) & ~ADC_CS;
>LLL + begin
>LLL + if (tick)
>LLL + din2 <= din1 & dv[3];
>LLL + adc_sampled <= dine & din2;
>LLL + end
LLL: My understanding of the datasheet says, that the ADC samples the analog input one
LLL: tick later than din1. Please review.
>
> reg [1:0] din_sr;
> always @(posedge clk)
> @@ -65,7 +76,7 @@
> always @(posedge clk)
> if (reset)
> adc_add <= ~0;
>HHH - else if(dout1 & &dv[1])
>HHH + else if(dout1 & dv[1])
HHH: dv[1] is a bit, no AND gate needed.
> adc_add <= adc_add + na;
>
> reg [2:0] ad;
> @@ -77,37 +88,29 @@
> if(din1 | reset)
> adc_channel <= ad;
>
>LLL - always @(posedge clk)
>LLL - if(reset)
>LLL - dv <= 0;
>LLL - else if(mtick & doute)
>LLL - dv <= {1'b1, dv[1:2]};
> -
> reg p;
> always @(posedge clk)
> if(mtick & doute | reset)
> - p<= 0;
> + p <= 0;
> else if(adc_sampled)
> p <= 1;
>
> reg v;
> always @(posedge clk)
>HHH - v <= mtick & doute & ~ADC_CS & p;
>HHH - always @(posedge clk)
>HHH - adc_valid <= v;
>HHH + {adc_valid, v} <= {v, mtick & doute & p};
HHH: Avoid reference to output registers.
HHH: ADC_CS asserted is implied in doute.
HHH: Too many always blocks cost simulation time.
>
> reg [11:0] dataa1;
> always @(posedge clk)
>HHH - if (doute & ~ADC_CS)
>HHH + if (doute)
> dataa1 <= {dataa1[10:0], ADC_DOUT[1]};
>
> reg [11:0] dataa2;
> always @(posedge clk)
>HHH - if (doute & ~ADC_CS)
>HHH + if (doute)
> dataa2 <= {dataa2[10:0], ADC_DOUT[2]};
>
> always @(posedge clk)
>HHH - if(v | reset)
>HHH + if(v | reset) // TODO: Why the reset?
> begin
> adc_d1 <= dataa1;
> adc_d2 <= dataa2;
> Index: stein/altera/stein_l2trig.v
> ===================================================================
> --- stein/altera/stein_l2trig.v (revision 3384)
> +++ stein/altera/stein_l2trig.v (revision 3385)
> @@ -7,20 +7,26 @@
> input clk,
> input tokene, // tokens are valid
> input [31:0] tokens, // tokens themselves
>BBB + input [7:0] dtime, // trigger delta time
> input [3:0] thsp, // threshold for small pixel
> input [3:0] thlp, // threshold for large pixel
> input [1:0] thbp, // threshold for background pixel
> input [5:0] thsum, // threshold for the sum of the pixel
>BBBB + input [7:0] th_dtime,
> output reg [3:0] sp, // amount of small pixel set
> output reg [3:0] lp, // amount of large pixel set
> output reg [1:0] bp, // amount of background pixel set
> output reg [4:0] sum,// sum of pixel set
>HHH + output reg too_fast,
>HHH + output reg too_few,
>HHH + output reg too_many,
>HHH + output reg too_many_small,
>HHH + output reg too_many_large,
>HHH + output reg too_many_bg,
HHH: These events shall be counted.
HHH: feed nack & too_* into the backend counter array.
> output reg ack, // do digitizing
> output reg nack // do not digitizing
> );
>
>BBB - reg tick;
>BBB -
> wire [31:0] tosp = tokens & mask_sp;
> wire [31:0] tolp = tokens & mask_lp;
> wire [31:0] tobp = tokens & mask_bp;
> @@ -32,31 +38,44 @@
> countbits #(.N(32), .M(4)) counter_lp(.i(tolp), .q(clp));
> countbits #(.N(32), .M(2)) counter_bp(.i(tobp), .q(cbp));
>
>BBB + reg [1:2] tick;
> always @(posedge clk)
> begin
> if (tokene)
> begin
>BBB - tick <= 1;
>BBB + tick <= 2'b10;
> sp <= csp;
> lp <= clp;
> bp <= cbp;
> sum <= csp + clp + cbp;
> end
>BBB - else if (tick)
>BBB + else if (tick[1])
>BBB + tick <= 2'b01;
>BBB + else
>BBB + tick <= 0;
>BBB +
>BBB + if (tick[1])
> begin
>BBB - tick <= 0;
>BBB - if (csp <= thsp & clp <= thlp & cbp <= thbp & sum <= thsum)
>BBB - ack <= 1;
>BBB - else
>BBB - nack <=1;
>BBB + too_few <= sum == 0;
>BBB + too_fast <= dtime < th_dtime;
>BBB + too_many <= sum > thsum;
>BBB + too_many_small <= sp > thsp;
>BBB + too_many_large <= lp > thlp;
>BBB + too_many_bg <= bp > thbp;
> end
>BBB +
>BBB + if (too_few | too_fast| too_many | too_many_small | too_many_large | too_many_bg)
>BBB + begin
>BBB + nack <= tick[2];
>BBB + ack <= 0;
>BBB + end
> else
> begin
>BBB - tick <= 0;
>BBB - ack <= 0;
>BBB + ack <= tick[2];
> nack <= 0;
> end
> end
> +
> endmodule // stein_l2trig
>
> module stein_l2classifier
> Index: arena/altera/idef-x/ix.v
> ===================================================================
> --- arena/altera/idef-x/ix.v (revision 3384)
> +++ arena/altera/idef-x/ix.v (revision 3385)
> @@ -208,6 +208,7 @@
>
>
> module ix_slow_control
>EEE + #(parameter DOUT_DELAY=0)
> (
> input clk,
> input reset,
> @@ -273,10 +274,19 @@
> else if (tick & STROBE)
> n <= n - 1;
>
>EEE + reg [0:DOUT_DELAY] dout_tick;
> reg dout;
> always @(posedge clk)
> if (tick & STROBE)
>EEE - dout <= DOUT;
>EEE + begin
>EEE + dout <= DOUT;
>EEE + dout_tick <= (1<<DOUT_DELAY)-1;
>EEE + end
>EEE + else if (dout_tick[DOUT_DELAY])
>EEE + begin
>EEE + dout <= DOUT;
>EEE + dout_tick <= dout_tick>>1;
>EEE + end
>
> always @(posedge clk)
> if (tick & ~STROBE)
> @@ -460,7 +470,8 @@
> input enable,
> input extrig,
> input [7:0] delay,
>JJJ - output reg tout
>JJJ + output reg tout,
>JJJ + output tinn
> );
>
> reg [5:0] tt;
> @@ -506,6 +517,8 @@
> always @(posedge clk)
> tout <= enable & ((tin_cnt==1) | extrig);
>
>JJJ + assign tinn = tt[1];
>JJJ +
> endmodule // debounce
>
> module ix_acquire
> Index: arena/altera/idef-x/tarena_test.v
> ===================================================================
> --- arena/altera/idef-x/tarena_test.v (revision 3384)
> +++ arena/altera/idef-x/tarena_test.v (revision 3385)
> @@ -201,7 +201,7 @@
> spi.cmdp(dut.TARENA_ADDR+13, 16'b xxxxxx_0000000100);
> spi.cmdp(dut.TARENA_ADDR+14, 16'b xxxxxx_0000000010);
> #100;
>BBB - spi.cmdp(IXADDR+1, {1'b0, 3'd 1, 8'd 50});
>BBB + spi.cmdp(IXADDR+1, {4'd15, 1'b0, 3'd 1, 8'd 50});
> spi.cmdp(IXADDR+7, {6'd 32, 2'd 3, 4'd 15, 4'd 15});
> ix_reset;
> spi.cmdp(dut.front.MCONF_ADDR+2, 16'h 0089);
> @@ -225,11 +225,15 @@
> ix.pulse(7,300);
> ix.trigger;
> #100 spi.verbose = 1;
>BBB - repeat(50) spi.frame('h 8000);
>BBB + repeat(40) spi.frame('h 8000);
> ix.noise;
> ix.pulse(0,500);
> ix.trigger;
> repeat(50) spi.frame('h 8000);
>HHH + ix.noise;
>HHH + ix.tokens = 0;
>HHH + ix.TRIG = 1;
>HHH + repeat(50) spi.frame('h 8000);
HHH: Simulate an event without any tokens.
> spi.cmdp(IXADDR+1, {1'b1, 3'd 1, 8'd 50});
> ix.noise;
> ix.pulse(6,400);
> @@ -237,7 +241,7 @@
> ix.pulse(8,400);
> ix.pulse(9,400);
> ix.trigger;
> - repeat(150) spi.frame('h 8000);
> + repeat(250) spi.frame('h 8000);
> $finish;
> end
>
> Index: arena/altera/idef-x/tarena.v
> ===================================================================
> --- arena/altera/idef-x/tarena.v (revision 3384)
> +++ arena/altera/idef-x/tarena.v (revision 3385)
> @@ -17,11 +17,11 @@
> output reg [15:0] rd,
>
> input TRIG,
> - output reg STROBE,
> - output reg STROBEn,
> - output reg RD,
> - output reg SC,
> - output reg DIN,
> + output reg STROBE,
> + output reg STROBEn,
> + output reg RD,
> + output reg SC,
> + output reg DIN,
> input DOUT,
>
> output TEST,
> @@ -47,7 +47,9 @@
> output [3:1] fifo_push,
> input [3:1] fifo_full,
> output [15:0] fifo1_size,
> - output [15:0] fifo2_size
> + output [15:0] fifo2_size,
> +
> + output hss
> );
>
> wire strobe, read, sc, din;
> @@ -165,7 +167,7 @@
> endmodule
>
> module step_ix
>EEE - #(parameter FO=1, DOUT_DELAY=2)
>EEE + #(parameter FO=1, DOUT_DELAY=2, AOUT_DELAY=1)
> (
> input clk,
> input reset,
> @@ -238,7 +240,7 @@
> assign {ix_strobe[1], ix_din[1]} = 0;
>
> // needs to accout for the delay of two clock cycles.
>EEE - ix_slow_control s
>EEE + ix_slow_control #(.DOUT_DELAY(DOUT_DELAY)) s
> (.clk(clk), .reset(reset | ww[0]),
> .we(ww[2]|ww[3]), .wa(wa[0]), .wp(wp), .wd(wd),
> .re(ree[1]), .rd(rdd[1]),
> @@ -277,12 +279,13 @@
> wire [7:0] read_delay;
> wire [2:0] acq_time;
> wire all;
> -
>BBB - conf_reg #(.NB(12)) c1
>BBB + wire [3:0] th_dtime;
> +
>BBB + conf_reg c1
> (.mclk(clk),
> .we(ww[1]), .wp(wp), .wd(wd),
> .re(ree[2]), .rd(rdd[2]),
>BBB - .conf({all, acq_time, read_delay}) );
>BBB + .conf({th_dtime, all, acq_time, read_delay}) );
>
> // L2 trigger configuration
> wire [3:0] thsp;
> @@ -305,22 +308,38 @@
> wire [31:0] token;
> wire ack;
> wire nack;
> -
>EEE - stein_ix_controller #(.MCLK(96)) stein_ix_controller
>CCC + wire s_en, s_ack;
>CCC + wire [15:0] s_data;
> +
>EEE + stein_ix_controller
>EEE + #(.MCLK(96), .DOUT_DELAY(DOUT_DELAY), .AOUT_DELAY(AOUT_DELAY))
>EEE + stein_ix_controller
> (.clk(clk), .reset(reset | ww[0]), .enable_acquire(enable),
> .read_delay(read_delay), .acq_time(acq_time),
>AAA - .all(all), .timestamp(clock[18:0]),
>AAA + .all(all), .timestamp(clock),
> .l2cls(l2cls), .e_start(e_start), .e_next(e_next), .e_done(e_done), .data(data),
> .baseline(baseline),
>BBB - .thsp(thsp), .thlp(thlp), .thbp(thbp), .thsum(thsum),
>BBB + .thsp(thsp), .thlp(thlp), .thbp(thbp), .thsum(thsum), .th_dtime({4'b0,th_dtime}),
> .TRIG(TRIG), .DOUT(DOUT), .STROBE(ix_strobe[3]), .RD(ix_rd[3]), .DIN(ix_din[3]),
> .adc_sampled(adc_sampled), .adc_valid(adc_valid), .adc_channel(adc_channel),
> .adc_d1(adc_d1), .adc_d2(adc_d2), .adc_chn(adc_chn), .adc_request(ix_adc_req),
> .fifo_full(fifof), .token(token), .ack(ack), .nack(nack),
>CCC - .hss(), .DEBUG() );
>CCC + .stream_en(s_en), .stream_ack(s_ack), .stream_data(s_data),
>CCC + .DEBUG() );
>
> assign ix_sc[3] = 0;
>CCC +
>CCC +`ifdef ARxSTREAM
>
>CCC + serialize serializer
>CCC + (
>CCC + .mclk(clk),
>CCC + .data_e(s_en), .data_ack(s_ack), .data(s_data),
>CCC + .cntr_e(1'b0), .cntr_ack(), .cntr(16'b0),
>CCC + .sclk(clk), .out(hss)
>CCC + );
>CCC +
>CCC +`endif
>
> // Data packager
>
> @@ -359,7 +378,7 @@
> (.clk(clk), .reset(reset), .go(ww[4]),
> .re(ree[4]), .rd(rdd[4]),
> .adc_channel(adc_channel),
>MMM - .adc_v(adc_valid), .adc_d1(adc_d1), .adc_d2(adc_d2),
>MMM + .adc_s(adc_sampled), .adc_v(adc_valid), .adc_d1(adc_d1), .adc_d2(adc_d2),
> .adc_req(adc_request) );
>
>
> @@ -428,6 +447,7 @@
>
> input [2:0] adc_channel,
>
>MMM + input adc_s,
> input adc_v,
> input [11:0] adc_d1,
> input [11:0] adc_d2,
> @@ -435,7 +455,26 @@
> );
>
> reg [3:0] c;
>MMM - wire adc_val = adc_v & c=={1'b0, adc_channel};
>MMM + reg good;
>MMM +
>MMM + always @(posedge clk)
>MMM + begin
>MMM + adc_req <= 'h ff << c;
>MMM +
>MMM + if (reset)
>MMM + c <= 8;
>MMM + else if (go)
>MMM + c <= 0;
>MMM + else if (adc_s & c=={1'b0, adc_channel})
>MMM + c <= c+1;
>MMM +
>MMM + if (reset | go)
>MMM + good <= 0;
>MMM + else if (adc_s)
>MMM + good <= c=={1'b0, adc_channel};
>MMM + end
>MMM +
>MMM + wire adc_val = adc_v & good;
MMM: use adc_sampled to revoke adc_requests as early as possible.
>
> reg ree;
> always @(posedge clk)
> @@ -460,16 +499,6 @@
> rd <= 0;
> end
>
>MMM - always @(posedge clk)
>MMM - begin
>MMM - adc_req <= 8'h01 << c;
>MMM - if(reset)
>MMM - c <= 8;
>MMM - else if(go)
>MMM - c <= 0;
>MMM - else if(adc_val)
>MMM - c <= c + 1;
>MMM - end
> -
> +
> endmodule // adc_housekeeping
>
> Index: arena/altera/Makefile
> ===================================================================
> --- arena/altera/Makefile (revision 3384)
> +++ arena/altera/Makefile (revision 3385)
> @@ -16,7 +16,7 @@
>
> varena_FLAGS = -DVARENA -s varena_test
> iarena_FLAGS = -DIARENA -s iarena_test -DNOINVTRIG
>CCC -tarena_FLAGS = -DTARENA -s tarena_test
>CCC +tarena_FLAGS = -DTARENA -s tarena_test -DARxSTREAM
> sarena_FLAGS = -DSARENA -s sarena_test
> aarena_FLAGS = -DAARENA -s aarena_test
>
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