thhor_crs/fpga/thhor_crs.qsf

# -*- tcl -*-
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		irena_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY quartus

set_global_assignment -name DEVICE 10CL025YE144I7G
set_global_assignment -name TOP_LEVEL_ENTITY thhor_crs
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name MISC_FILE thhor_crs.dpf
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name CRC_ERROR_CHECKING ON
set_global_assignment -name FORCE_CONFIGURATION_VCCIO OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name EDA_SIMULATION_TOOL "Custom Verilog HDL"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS OFF
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

############ Left 3.3V

set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to xclk
set_location_assignment PIN_22 -to xclk

set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_ssel
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_sck
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_mosi
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_miso

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to spi_ssel
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to spi_miso
set_instance_assignment -name FAST_INPUT_REGISTER ON -to spi_mosi

set_location_assignment PIN_8 -to spi_ssel
set_location_assignment PIN_11 -to spi_sck 
set_location_assignment PIN_13 -to spi_mosi
set_location_assignment PIN_10 -to spi_miso

############# right 2.5V

# LVDS spacewire

set_instance_assignment -name IO_STANDARD LVDS -to S_OUT
set_instance_assignment -name IO_STANDARD LVDS -to D_OUT
set_instance_assignment -name IO_STANDARD LVDS -to S_IN
set_instance_assignment -name IO_STANDARD LVDS -to D_IN

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to S_OUT
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to D_OUT

set_location_assignment PIN_87 -to S_OUT
set_location_assignment PIN_86 -to "S_OUT(n)"
set_location_assignment PIN_103 -to D_OUT
set_location_assignment PIN_101 -to "D_OUT(n)"
set_location_assignment PIN_91 -to S_IN
set_location_assignment PIN_90 -to "S_IN(n)"

# Pressure Sensor

set_instance_assignment -name IO_STANDARD "2.5 V" -to pt_Dout
set_instance_assignment -name IO_STANDARD "2.5 V" -to pt_Din
set_instance_assignment -name IO_STANDARD "2.5 V" -to pt_MCLK
set_instance_assignment -name IO_STANDARD "2.5 V" -to pt_SCLK

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to pt_Din
set_instance_assignment -name FAST_INPUT_REGISTER ON -to pt_Dout
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to pt_MCLK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to pt_SCLK

set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to pt_DOUT
set_instance_assignment -name CURRENT_STRENGTH_NEW "8mA" -to pt_Din
set_instance_assignment -name CURRENT_STRENGTH_NEW "8mA" -to pt_MCLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "8mA" -to pt_SCLK

set_instance_assignment -name SLEW_RATE 0 -to pt_Din
set_instance_assignment -name SLEW_RATE 0 -to pt_MCLK
set_instance_assignment -name SLEW_RATE 0 -to pt_SCLK

set_location_assignment PIN_77 -to pt_Dout
set_location_assignment PIN_80 -to pt_Din
set_location_assignment PIN_83 -to pt_MCLK
set_location_assignment PIN_76 -to pt_SCLK

########## bottom 3.3V

set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ADC_nCS	
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ADC_SCK	
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ADC_DIN	
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ADC_DOUT

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ADC_nCS	
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ADC_SCK	
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ADC_DIN	
set_instance_assignment -name FAST_INPUT_REGISTER ON  -to ADC_DOUT

set_location_assignment PIN_66 -to ADC_nCS[0]
set_location_assignment PIN_69 -to ADC_SCK[0] 
set_location_assignment PIN_67 -to ADC_DIN[0] 
set_location_assignment PIN_68 -to ADC_DOUT[0]

set_location_assignment PIN_58 -to ADC_nCS[1]
set_location_assignment PIN_65 -to ADC_SCK[1] 
set_location_assignment PIN_59 -to ADC_DIN[1] 
set_location_assignment PIN_60 -to ADC_DOUT[1]

set_location_assignment PIN_46 -to ADC_nCS[2]
set_location_assignment PIN_51 -to ADC_SCK[2] 
set_location_assignment PIN_49 -to ADC_DIN[2] 
set_location_assignment PIN_50 -to ADC_DOUT[2]

set_location_assignment PIN_39 -to ADC_nCS[3]
set_location_assignment PIN_44 -to ADC_SCK[3] 
set_location_assignment PIN_42 -to ADC_DIN[3] 
set_location_assignment PIN_43 -to ADC_DOUT[3]

########## Spares 3.3V left, top

set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P33
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to P33
set_instance_assignment -name FAST_INPUT_REGISTER ON -to P33
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to P33

set_location_assignment PIN_6  -to P33[0]
set_location_assignment PIN_7  -to P33[1]
set_location_assignment PIN_28 -to P33[2]
set_location_assignment PIN_31 -to P33[3]
set_location_assignment PIN_32 -to P33[4]
set_location_assignment PIN_33 -to P33[5]
set_location_assignment PIN_71 -to P33[6]
set_location_assignment PIN_72 -to P33[7]


########## Spares 2.5V right, bottom

set_instance_assignment -name IO_STANDARD "2.5 V" -to P25
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to P25
set_instance_assignment -name FAST_INPUT_REGISTER ON -to P25
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to P25

set_location_assignment PIN_106 -to P25[0]
set_location_assignment PIN_111 -to P25[1]
set_location_assignment PIN_112 -to P25[2]
set_location_assignment PIN_113 -to P25[3]
set_location_assignment PIN_114 -to P25[4]
set_location_assignment PIN_115 -to P25[5]
set_location_assignment PIN_119 -to P25[6]
set_location_assignment PIN_120 -to P25[7]
set_location_assignment PIN_121 -to P25[8]
set_location_assignment PIN_125 -to P25[9]
set_location_assignment PIN_132 -to P25[10]
set_location_assignment PIN_133 -to P25[11]
set_location_assignment PIN_135 -to P25[12]
set_location_assignment PIN_136 -to P25[13]
set_location_assignment PIN_137 -to P25[14]
set_location_assignment PIN_141 -to P25[15]
set_location_assignment PIN_142 -to P25[16]
set_location_assignment PIN_143 -to P25[17]
set_location_assignment PIN_144 -to P25[18]

########## Sources

set_global_assignment -name VERILOG_FILE thhor_crs.v
set_global_assignment -name VERILOG_FILE solo/altera/spi_slave.v
set_global_assignment -name VERILOG_FILE solo/altera/frontend.v
set_global_assignment -name VERILOG_FILE solo/altera/packetfifo.v
set_global_assignment -name VERILOG_FILE solo/altera/mega/spififo.v
set_global_assignment -name VERILOG_FILE solo/altera/conf_reg.v
set_global_assignment -name VERILOG_FILE solo/altera/countbits.v
set_global_assignment -name VERILOG_FILE solo/altera/serializer.v
set_global_assignment -name VERILOG_FILE solo/altera/secondcyclone.v
set_global_assignment -name VERILOG_FILE solo/dorn/altera/thhor_core.v
set_global_assignment -name VERILOG_FILE solo/dorn/altera/stis_ana_core.v
set_global_assignment -name VERILOG_FILE solo/dorn/altera/dorn.v
set_global_assignment -name VERILOG_FILE solo/dorn/altera/multiply.v
set_global_assignment -name VERILOG_FILE solo/dorn/altera/divider.v
set_global_assignment -name VERILOG_FILE solo/nm64/altera/nmcounter.v
set_global_assignment -name VERILOG_FILE solo/dorn/altera/dmem.v
set_global_assignment -name VERILOG_FILE solo/altera/mem.v
set_global_assignment -name VERILOG_FILE solo/altera/itof.v
set_global_assignment -name VERILOG_FILE solo/irena/altera/ms5540c.v
set_global_assignment -name VERILOG_FILE solo/altera/adc128s102.v

set_global_assignment -name VERILOG_MACRO "TARGET_ALTERA=1"
set_global_assignment -name VERILOG_MACRO "TARGET_10C25=1"
set_global_assignment -name VERILOG_MACRO "THHOR=1"
set_global_assignment -name VERILOG_MACRO "INFERRED_SRAM=1"
set_global_assignment -name VERILOG_MACRO "WITH_FULL_L1_CONF=1"
set_global_assignment -name VERILOG_MACRO "WITH_FULL_L2_CONF=1"
set_global_assignment -name VERILOG_MACRO "WITH_FULL_L3_CONF=1"
set_global_assignment -name VERILOG_MACRO "ANA_WITHOUT_SERIALIZER=1"
set_global_assignment -name VERILOG_MACRO "SPARSE_TRIG_EN=1"
set_global_assignment -name VERILOG_MACRO "L2_AHEPAM=1"
set_global_assignment -name VERILOG_MACRO "WITH_SPI_SSEL=1"
set_global_assignment -name VERILOG_MACRO "AX_PORT=1"
set_global_assignment -name VERILOG_MACRO "SER_FIFO_ALTERA=1"
set_global_assignment -name VERILOG_MACRO "SPI_TIMEOUT_1024=1"