Stephan I. Böttcher
0c020d3380
thhor_csa: extended board frame
2026-05-05 18:59:16 +02:00
Stephan I. Böttcher
bc82d2658f
pcb: fix XO53 oscillator enable pin
2026-03-25 20:10:26 +01:00
Stephan I. Böttcher
b39371e370
layout: fix soldermask of bottom board frame
2026-03-25 08:12:56 +01:00
Stephan I. Böttcher
f6517860d7
fix pos Vbias HK
...
The offset R for pos Vbias must connect to a negative supply
Use VssH instead of Vadc
Layout Version V2 2026-03-25
Delete stray trace (complained about by Leiton Review)
2026-03-25 07:45:04 +01:00
Stephan I. Böttcher
d8e15f33e0
fix drill diameter of the Omnetics footprint
2026-03-19 14:54:20 +01:00
Stephan I. Böttcher
090edaa2d1
part values
2026-01-06 17:55:47 +01:00
Stephan I. Böttcher
0b3ac45932
layer order
2026-01-06 17:42:04 +01:00
Stephan I. Böttcher
bb82c00fec
swap TxE and nCS, to use XDIR for TxE
2026-01-05 12:21:43 +01:00
Stephan I. Böttcher
413be88d6b
disable Rx when Tx
2026-01-05 11:40:02 +01:00
Stephan I. Böttcher
ee55a919ce
U6 value TI part
2025-12-31 11:52:07 +01:00
Stephan I. Böttcher
dfdf165d3b
U6 value
2025-12-31 01:20:11 +01:00
Stephan I. Böttcher
7b36d564ed
add U6: AND gate to drop DCLK while reading the bitfile from flash
2025-12-31 01:16:21 +01:00
Stephan I. Böttcher
c3dba4356d
layout: refdes positions, soldermask
2025-12-22 02:09:20 +01:00
Stephan I. Böttcher
a908ac1c8f
fpga pinout, with fixes on the schematics and layout
2025-12-21 23:27:15 +01:00
Stephan I. Böttcher
8aaa6e8c2f
proper T and Θ in pcb
2025-12-20 23:12:45 +01:00
Stephan I. Böttcher
0979fd3819
add blocking caps to use the remaining space
2025-12-20 23:00:25 +01:00
Stephan I. Böttcher
00d93d5483
frame element, pngs
2025-12-20 20:56:41 +01:00
Stephan I. Böttcher
db8dae5f84
via frame
2025-12-20 20:42:03 +01:00
Stephan I. Böttcher
fb0ff6f300
layout complete
2025-12-20 20:04:44 +01:00
Stephan I. Böttcher
773d85528a
layout …
2025-12-20 11:59:52 +01:00
Stephan I. Böttcher
8470575aa7
shaper layout from leia
2025-12-20 05:02:39 +01:00
Stephan I. Böttcher
ddbeb79950
all FPGA blocking caps, unused pins
2025-12-19 01:01:32 +01:00
Stephan I. Böttcher
8fac9f59d6
XO53 placement
2025-12-18 18:04:14 +01:00
Stephan I. Böttcher
37108173f3
FPGA placed, two sides connected
2025-12-18 03:52:01 +01:00
Stephan I. Böttcher
a476d77e83
XIO and XPLL layout
2025-12-17 21:44:57 +01:00
Stephan I. Böttcher
272b7fc6f1
layout sepic and Vbias
2025-12-17 20:51:44 +01:00
