//
// ALTERA megafunctions for plls and simulation models

`ifdef SIMULATION

`timescale 1ns/1ps

module pll192
  (
   input      inclk0, // 12 MHz
   output reg c0, // 192 MHz
   output reg c1, // 96 MHz
   output reg c2, // 64 MHz
   output reg c3, // 32 MHz
   output reg c4, // 16 MHz
   output reg locked
   );

   always @(posedge inclk0)
     begin
        #0     c0 = 1;
        #2.604 c0 = 0; // 1/192MHz = 5.208ns -> 2.604ns
        repeat (15) // still 19 or 16?
                    // 20*4.167(old value) = 83.34ns -> 83.34/5.208 = 16
          begin
             #2.604 c0 = 1;
             #2.604 c0 = 0;
          end
     end
   always @(posedge inclk0)
     begin
        #2.604 c1 = 1;
        #5.208 c1 = 0; // 1/96MHz = 10.417 -> 5.208ns
        repeat (7) //still 39?
          begin
             #5.208 c1 = 1;
             #5.208 c1 = 0;
          end
        locked <= 1;
     end
   always @(posedge inclk0)
     begin
        #0      c2 = 1;
        #7.8125 c2 = 0; // 1/64MHz = 15.625 -> 7.8125ns
        repeat (15)
          begin
             #7.8215 c2 = 1;
             #7.8215 c2 = 0;
          end
     end
   always @(posedge inclk0)
     begin
        #7.8125  c3 = 1;
        #15.625  c3 = 0; // 1/32MHz = 31.25 -> 15.625ns
        repeat (7)
          begin
             #15.625 c3 = 1; 
             #15.625 c3 = 0;
          end
     end
   always @(posedge inclk0)
     begin
        #15.625 c4 = 1;
        #31.25  c4 = 0; // 1/16MHz = 62.5 -> 31.25ns
        repeat (3)
          begin
             #31.25 c4 = 1;
             #31.25 c4 = 0;
          end
     end

endmodule // pll192

`else
 `ifndef PLL_LOW_LEVEL

module pll192 
  (
   input  inclk0,
   output c0, c1, c2, c3, c4,
   output locked
   );

   // inclk 12 MHz
   //
   //  "192.000000"
   //  "96.000000"
   //  "64.000000"
   //  "32.000000"
   //  "16.000000"

   altpll altpll_component 
     (
      .inclk ({1'b0, inclk0}),
      .clk ({c4, c3, c2, c1, c0}),
      .locked (locked),
      .activeclock (),
      .areset (1'b0),
      .clkbad (),
      .clkena ({6{1'b1}}),
      .clkloss (),
      .clkswitch (1'b0),
      .configupdate (1'b0),
      .enable0 (),
      .enable1 (),
      .extclk (),
      .extclkena ({4{1'b1}}),
      .fbin (1'b1),
      .fbmimicbidir (),
      .fbout (),
      .fref (),
      .icdrclk (),
      .pfdena (1'b1),
      .phasecounterselect ({4{1'b1}}),
      .phasedone (),
      .phasestep (1'b1),
      .phaseupdown (1'b1),
      .pllena (1'b1),
      .scanaclr (1'b0),
      .scanclk (1'b0),
      .scanclkena (1'b1),
      .scandata (1'b0),
      .scandataout (),
      .scandone (),
      .scanread (1'b0),
      .scanwrite (1'b0),
      .sclkout0 (),
      .sclkout1 (),
      .vcooverrange (),
      .vcounderrange () 
      );
   
   defparam
     altpll_component.bandwidth_type = "AUTO",
     altpll_component.clk0_divide_by = 1,
     altpll_component.clk0_duty_cycle = 50,
     altpll_component.clk0_multiply_by = 16,
     altpll_component.clk0_phase_shift = "0",
     altpll_component.clk1_divide_by = 1,
     altpll_component.clk1_duty_cycle = 50,
     altpll_component.clk1_multiply_by = 8,
     altpll_component.clk1_phase_shift = "2600",
     altpll_component.clk2_divide_by = 3,
     altpll_component.clk2_duty_cycle = 50,
     altpll_component.clk2_multiply_by = 16,
     altpll_component.clk2_phase_shift = "0",
     altpll_component.clk3_divide_by = 3,
     altpll_component.clk3_duty_cycle = 50,
     altpll_component.clk3_multiply_by = 8,
     altpll_component.clk3_phase_shift = "7800",
     altpll_component.clk4_divide_by = 3,
     altpll_component.clk4_duty_cycle = 50,
     altpll_component.clk4_multiply_by = 4,
     altpll_component.clk4_phase_shift = "23440",
     altpll_component.compensate_clock = "CLK0",
     altpll_component.inclk0_input_frequency = 83333,
     altpll_component.intended_device_family = "Cyclone 10 LP",
     altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll192",
     altpll_component.lpm_type = "altpll",
     altpll_component.operation_mode = "NORMAL",
     altpll_component.pll_type = "AUTO",
     altpll_component.port_activeclock = "PORT_UNUSED",
     altpll_component.port_areset = "PORT_UNUSED",
     altpll_component.port_clkbad0 = "PORT_UNUSED",
     altpll_component.port_clkbad1 = "PORT_UNUSED",
     altpll_component.port_clkloss = "PORT_UNUSED",
     altpll_component.port_clkswitch = "PORT_UNUSED",
     altpll_component.port_configupdate = "PORT_UNUSED",
     altpll_component.port_fbin = "PORT_UNUSED",
     altpll_component.port_inclk0 = "PORT_USED",
     altpll_component.port_inclk1 = "PORT_UNUSED",
     altpll_component.port_locked = "PORT_USED",
     altpll_component.port_pfdena = "PORT_UNUSED",
     altpll_component.port_phasecounterselect = "PORT_UNUSED",
     altpll_component.port_phasedone = "PORT_UNUSED",
     altpll_component.port_phasestep = "PORT_UNUSED",
     altpll_component.port_phaseupdown = "PORT_UNUSED",
     altpll_component.port_pllena = "PORT_UNUSED",
     altpll_component.port_scanaclr = "PORT_UNUSED",
     altpll_component.port_scanclk = "PORT_UNUSED",
     altpll_component.port_scanclkena = "PORT_UNUSED",
     altpll_component.port_scandata = "PORT_UNUSED",
     altpll_component.port_scandataout = "PORT_UNUSED",
     altpll_component.port_scandone = "PORT_UNUSED",
     altpll_component.port_scanread = "PORT_UNUSED",
     altpll_component.port_scanwrite = "PORT_UNUSED",
     altpll_component.port_clk0 = "PORT_USED",
     altpll_component.port_clk1 = "PORT_USED",
     altpll_component.port_clk2 = "PORT_USED",
     altpll_component.port_clk3 = "PORT_USED",
     altpll_component.port_clk4 = "PORT_USED",
     altpll_component.port_clk5 = "PORT_UNUSED",
     altpll_component.port_clkena0 = "PORT_UNUSED",
     altpll_component.port_clkena1 = "PORT_UNUSED",
     altpll_component.port_clkena2 = "PORT_UNUSED",
     altpll_component.port_clkena3 = "PORT_UNUSED",
     altpll_component.port_clkena4 = "PORT_UNUSED",
     altpll_component.port_clkena5 = "PORT_UNUSED",
     altpll_component.port_extclk0 = "PORT_UNUSED",
     altpll_component.port_extclk1 = "PORT_UNUSED",
     altpll_component.port_extclk2 = "PORT_UNUSED",
     altpll_component.port_extclk3 = "PORT_UNUSED",
     altpll_component.self_reset_on_loss_lock = "OFF",
     altpll_component.width_clock = 5;

endmodule

`else // !`ifdef PLL_LOW_LEVEL

module pll192
  (
   input  inclk0;
   output c0, c1, c2, c3, c4;
   output locked;
   );
   
   altpll	altpll_component 
     (
      .inclk ({1'b0, inclk0}),
      .clk ({c4, c3, c2, c1, c0}),
      .locked (locked),
      .activeclock (),
      .areset (1'b0),
      .clkbad (),
      .clkena ({6{1'b1}}),
      .clkloss (),
      .clkswitch (1'b0),
      .configupdate (1'b0),
      .enable0 (),
      .enable1 (),
      .extclk (),
      .extclkena ({4{1'b1}}),
      .fbin (1'b1),
      .fbmimicbidir (),
      .fbout (),
      .fref (),
      .icdrclk (),
      .pfdena (1'b1),
      .phasecounterselect ({4{1'b1}}),
      .phasedone (),
      .phasestep (1'b1),
      .phaseupdown (1'b1),
      .pllena (1'b1),
      .scanaclr (1'b0),
      .scanclk (1'b0),
      .scanclkena (1'b1),
      .scandata (1'b0),
      .scandataout (),
      .scandone (),
      .scanread (1'b0),
      .scanwrite (1'b0),
      .sclkout0 (),
      .sclkout1 (),
      .vcooverrange (),
      .vcounderrange ()
      );

   defparam
     altpll_component.charge_pump_current_bits = 1,
     altpll_component.compensate_clock = "CLK0",
     altpll_component.inclk0_input_frequency = 83333,
 `ifdef CYCLONE10
     altpll_component.intended_device_family = "Cyclone 10 LP",
 `endif
     altpll_component.loop_filter_c_bits = 0,
     altpll_component.loop_filter_r_bits = 24,
     altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll192",
     altpll_component.lpm_type = "altpll",
     altpll_component.m = 32,
     altpll_component.m_initial = 1,
     altpll_component.m_ph = 0,
     altpll_component.n = 1,
     altpll_component.operation_mode = "NORMAL",
     altpll_component.pll_type = "AUTO",
     altpll_component.port_activeclock = "PORT_UNUSED",
     altpll_component.port_areset = "PORT_UNUSED",
     altpll_component.port_clkbad0 = "PORT_UNUSED",
     altpll_component.port_clkbad1 = "PORT_UNUSED",
     altpll_component.port_clkloss = "PORT_UNUSED",
     altpll_component.port_clkswitch = "PORT_UNUSED",
     altpll_component.port_configupdate = "PORT_UNUSED",
     altpll_component.port_fbin = "PORT_UNUSED",
     altpll_component.port_inclk0 = "PORT_USED",
     altpll_component.port_inclk1 = "PORT_UNUSED",
     altpll_component.port_locked = "PORT_USED",
     altpll_component.port_pfdena = "PORT_UNUSED",
     altpll_component.port_phasecounterselect = "PORT_UNUSED",
     altpll_component.port_phasedone = "PORT_UNUSED",
     altpll_component.port_phasestep = "PORT_UNUSED",
     altpll_component.port_phaseupdown = "PORT_UNUSED",
     altpll_component.port_pllena = "PORT_UNUSED",
     altpll_component.port_scanaclr = "PORT_UNUSED",
     altpll_component.port_scanclk = "PORT_UNUSED",
     altpll_component.port_scanclkena = "PORT_UNUSED",
     altpll_component.port_scandata = "PORT_UNUSED",
     altpll_component.port_scandataout = "PORT_UNUSED",
     altpll_component.port_scandone = "PORT_UNUSED",
     altpll_component.port_scanread = "PORT_UNUSED",
     altpll_component.port_scanwrite = "PORT_UNUSED",
     altpll_component.port_clk0 = "PORT_USED",
     altpll_component.port_clk1 = "PORT_USED",
     altpll_component.port_clk2 = "PORT_USED",
     altpll_component.port_clk3 = "PORT_USED",
     altpll_component.port_clk4 = "PORT_USED",
     altpll_component.port_clk5 = "PORT_UNUSED",
     altpll_component.port_clkena0 = "PORT_UNUSED",
     altpll_component.port_clkena1 = "PORT_UNUSED",
     altpll_component.port_clkena2 = "PORT_UNUSED",
     altpll_component.port_clkena3 = "PORT_UNUSED",
     altpll_component.port_clkena4 = "PORT_UNUSED",
     altpll_component.port_clkena5 = "PORT_UNUSED",
     altpll_component.port_extclk0 = "PORT_UNUSED",
     altpll_component.port_extclk1 = "PORT_UNUSED",
     altpll_component.port_extclk2 = "PORT_UNUSED",
     altpll_component.port_extclk3 = "PORT_UNUSED",
     altpll_component.self_reset_on_loss_lock = "OFF",
     altpll_component.vco_post_scale = 2,
     altpll_component.width_clock = 5,
     altpll_component.c0_high = 1,
     altpll_component.c0_initial = 1,
     altpll_component.c0_low = 1,
     altpll_component.c0_mode = "even",
     altpll_component.c0_ph = 0,
     altpll_component.c1_high = 2,
     altpll_component.c1_initial = 2,
     altpll_component.c1_low = 2,
     altpll_component.c1_mode = "even",
     altpll_component.c1_ph = 0,
     altpll_component.c2_high = 3,
     altpll_component.c2_initial = 1,
     altpll_component.c2_low = 3,
     altpll_component.c2_mode = "even",
     altpll_component.c2_ph = 0,
     altpll_component.c3_high = 6,
     altpll_component.c3_initial = 4,
     altpll_component.c3_low = 6,
     altpll_component.c3_mode = "even",
     altpll_component.c3_ph = 0,
     altpll_component.c4_high = 12,
     altpll_component.c4_initial = 10,
     altpll_component.c4_low = 12,
     altpll_component.c4_mode = "even",
     altpll_component.c4_ph = 0,
     altpll_component.clk0_counter = "c0",
     altpll_component.clk1_counter = "c1",
     altpll_component.clk2_counter = "c2",
     altpll_component.clk3_counter = "c3",
     altpll_component.clk4_counter = "c4";

endmodule

`endif // !`ifdef PLL_LOW_LEVEL
`endif // !`ifdef SIMULATION