VERILOG=/usr/bin/iverilog

VERILOGFLAGS = -v -DSIMULATION $($*_FLAGS)
%.vvp:
	$(VERILOG) $(VERILOGFLAGS) $(VFLAGS) -o $@ $^

vcd/%.fst: %.vvp
	$< -fst | tee $*.log

.PRECIOUS: vcd/%.fst

THHOR_CRS_SRC = thhor_crs.v pll.v 

thhor_crs.vvp: $(THHOR_CRS_SRC)
thhor_crs_FLAGS = -sthhor_crs_test -DTHHOR_CRS -DTHHOR_CRS_TEST

CYCLONE=10

ifeq ($(CYCLONE),10)
QUARTUS=/usr/local/quartus/intelFPGA_lite/20.1/quartus
else
QUARTUS=/usr/local/quartus/altera13.1/quartus
endif
export PATH:=$(QUARTUS)/bin:$(PATH):.

MAPFLGS = $(patsubst %, --verilog_macro="%",$($*_MAPDEFS) $(MAPDEFS))

QDIR=quartus
$(QDIR)/%.rbf: %.qpf %.qsf %.sdc
	quartus_map $< $(MAPFLGS)
	quartus_fit $<
	quartus_asm $<
	quartus_sta $<
	grep -i warning $(QDIR)/$*.*.rpt \
      | grep -v 'behaves as a Local Parameter Declaration because the module' \
      | grep -v 'truncated value with size 32 to match size of target' \
      |	sed  's/\.v([0-9]\+)/.v(…)/;s/File: .* Line: [0-9]\+$$//' \
      > $*.warnings
	grep '^; -' $(QDIR)/$*.sta.rpt >> $*.warnings || echo Timing OK

$(QDIR)/thhor_crs.rbf: thhor_crs.v pll.v