VERILOG=iverilog -gno-strict-parameter-declaration -Wno-declaration-after-use

VERILOGFLAGS = -v -DSIMULATION $($*_FLAGS)
%.vvp:
	$(VERILOG) $(VERILOGFLAGS) $(VFLAGS) -o $@ $^

vcd/%.fst: %.vvp
	$< -fst | tee $*.log

.PRECIOUS: vcd/%.fst

VPATH = solo/altera : solo/irena/altera: solo/irena/altera/adc128: \
        solo/dorn/altera : solo/nm64/altera

FRONTEND_FILES = frontend_test.v spi_slave.v frontend.v packetfifo.v conf_reg.v spififo_sim.v \
                 countbits.v serializer.v secondcyclone.v 
DORN_FILES = thhor_core.v stis_ana_core.v dorn.v multiply.v divider.v nmcounter.v dmem.v
IRENA_FILES = frontend_test.v mem.v itof.v ms5540c.v adc128s102.v pulser.v 

THHOR_CRS_SRC = thhor_crs.v $(FRONTEND_FILES) $(DORN_FILES) $(IRENA_FILES)

thhor_crs.vvp: $(THHOR_CRS_SRC)
vcd/thhor_crs.fst: sallen-key-pulse.hex
sallen-key-pulse.hex:
	ln -f solo/dorn/altera/$@
DORN_FLAGS =  -DWITH_FULL_L1_CONF -DWITH_FULL_L2_CONF -DWITH_FULL_L3_CONF \
              -DANA_WITHOUT_SERIALIZER -DSPARSE_TRIG_EN -DL2_AHEPAM
ARCH_FLAGS =  -DSTIS_ANA_JIG -DINFERRED_SRAM -DSER_FIFO_ALTERA -DWITH_SPI_SSEL

thhor_crs_FLAGS = -sthhor_crs_test -DTHHOR -DTHHOR_CRS_TEST -DAX_PORT \
         $(DORN_FLAGS) $(ARCH_FLAGS)

CYCLONE=10

ifeq ($(CYCLONE),10)
QUARTUS=/usr/local/quartus/intelFPGA_lite/20.1/quartus
else
QUARTUS=/usr/local/quartus/altera13.1/quartus
endif
export PATH:=$(QUARTUS)/bin:$(PATH):.

MAPFLGS = $(patsubst %, --verilog_macro="%",$($*_MAPDEFS) $(MAPDEFS))

QDIR=quartus
$(QDIR)/%.rbf: %.qpf %.qsf %.sdc
	quartus_map $< $(MAPFLGS)
	quartus_fit $<
	quartus_asm $<
	quartus_sta $<
	grep -i warning $(QDIR)/$*.*.rpt \
      | grep -v 'behaves as a Local Parameter Declaration because the module' \
      | grep -v 'truncated value with size 32 to match size of target' \
      |	sed  's/\.v([0-9]\+)/.v(…)/;s/File: .* Line: [0-9]\+$$//' \
      > $*.warnings
	grep '^; -' $(QDIR)/$*.sta.rpt >> $*.warnings || echo Timing OK

$(QDIR)/thhor_crs.rbf: thhor_crs.v pll.v