235 lines
6.8 KiB
Verilog
235 lines
6.8 KiB
Verilog
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module thhor_crs
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(
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input xclk,
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input spi_ssel, spi_sck, spi_mosi,
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output spi_miso,
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// Barometer
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output pt_MCLK, pt_SCLK, pt_Din,
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input pt_Dout,
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// ADCs
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output [3:0] ADC_nCS, ADC_SCK, ADC_DIN,
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input [3:0] ADC_DOUT,
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// LVDS
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output S_OUT, D_OUT,
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input S_IN, D_IN,
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// Spare Pins
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inout [18:0] P25,
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inout [7:0] P33
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);
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// no pll, the quarz is 32 MHz, as required.
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wire mclk = xclk;
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parameter ND=4;
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///FIFO definitions
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parameter NFIFO = 6;
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wire [NFIFO:1] fifo_push, fifo_full;
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wire [15:0] fifo[1:NFIFO], fsiz[1:NFIFO], fhma[1:NFIFO], fhva[1:NFIFO];
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wire [3:1] fifo_halffull;
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// packets that are generated on request only.
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parameter FIFO_MUX = 1;
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parameter FIFO_CNTR = 4;
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parameter FIFO_BATE = 5;
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parameter FIFO_HK = 6;
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wire we, wp, re;
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wire [13:0] wa;
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wire [15:0] wd, rd, resets, confs;
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wire stick;
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wire [14:0] states, strobes;
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wire [31:0] clock;
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reg [15:0] fifo_mux, fsiz_mux, fhma_mux, fhva_mux;
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reg fifo_mux_push;
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assign fifo_push[FIFO_MUX] = fifo_mux_push;
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assign fifo[FIFO_MUX] = fifo_mux;
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assign fsiz[FIFO_MUX] = fsiz_mux;
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assign fhma[FIFO_MUX] = fhma_mux;
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assign fhva[FIFO_MUX] = fhva_mux;
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assign fifo_full[NFIFO:4] = {(NFIFO-3){fifo_full[FIFO_MUX]}};
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integer ii;
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always @(posedge mclk)
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begin
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if (resets[4+FIFO_MUX])
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fsiz_mux <= 0;
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for (ii=4; ii<=NFIFO; ii=ii+1)
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if (fifo_push[ii])
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begin
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fifo_mux <= fifo[ii];
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fsiz_mux <= fsiz[ii];
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fhma_mux <= fhma[ii];
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fhva_mux <= fhva[ii];
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end
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fifo_mux_push <= |fifo_push[NFIFO:4];
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end
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frontend front
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(.mclk(mclk),
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.spi_ssel(~spi_ssel), .spi_sck(spi_sck), .spi_mosi(spi_mosi), .spi_miso(spi_miso),
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.sclk(mclk), .ARxC(S_IN), .ARxD(D_IN), .ATxC(S_OUT), .ATxD(D_OUT),
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.states(states), .strobes(strobes),
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.we(we), .wp(wp), .wa(wa), .wd(wd), .re(re), .rd(rd),
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.errors(), .stats(), .resets(resets), .confs(confs), .clock(),
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.conf3(),
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.fifo_push(fifo_push[3:1]), .fifo_full(fifo_full[3:1]),
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.fifo_halffull(fifo_halffull),
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.fifo1(fifo[1]), .fifo2(fifo[2]), .fifo3(fifo[3]),
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.fsiz1(fsiz[1]), .fsiz2(fsiz[2]), .fsiz3(fsiz[3]),
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.fhma1(fhma[1]), .fhma2(fhma[2]), .fhma3(fhma[3]),
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.fhva1(fhva[1]), .fhva2(fhva[2]), .fhva3(fhva[3]),
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.fsma1(64'b0), .fsma2(64'b0), .fsma3(64'b0),
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.tick(stick) );
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parameter NHIT = 3*ND + 1;
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wire [NHIT-1:0] counter_hit;
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parameter CNTR_ADDR = 'h 240;
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wire read_counters = we & wa[13:4]==CNTR_ADDR[13:4];
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assign fhma[FIFO_CNTR] = 16'h ffff;
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nm_counters #(.N(NHIT)) counters
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( .clk(mclk),
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.clear(resets[1] | read_counters & wa[2] & (~fifo_full[FIFO_CNTR] | ~wa[3])),
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.read(~fifo_full[FIFO_CNTR] & read_counters & wa[3]),
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.read_size(wa[1:0]),
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.clock(clock),
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.hit(counter_hit),
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.fifo_push(fifo_push[FIFO_CNTR]),
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.fifo(fifo[FIFO_CNTR]),
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.fifo_size(fsiz[FIFO_CNTR]),
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.fifo_head(fhva[FIFO_CNTR]) );
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parameter BATE_ADDR = 'h 0300; // … 'h 037f
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wire we_bate = we & (wa[13:7] == BATE_ADDR[13:7]);
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assign fhma[FIFO_BATE] = 'h ffff;
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pressure #(.CLK96(32_000_000)) bate
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( .clk96(mclk),
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.MCLK(pt_MCLK),
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.SCLK(pt_SCLK),
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.Din(pt_Din),
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.Dout(pt_Dout),
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.we(we_bate),
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.wa({1'b0, wa[6:0]}),
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.fifos(fsiz[FIFO_BATE]),
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.fifoh(fhva[FIFO_BATE]),
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.fifoe(fifo_push[FIFO_BATE]),
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.fifof(fifo_full[FIFO_BATE]),
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.fifo(fifo[FIFO_BATE]) );
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parameter HK_MAGIC = 16'h 5710;
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parameter SA_MAGIC = 16'h 5714;
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parameter EV_MAGIC = 16'h 5718;
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assign fhva[FIFO_HK] = HK_MAGIC;
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assign fhva[2] = EV_MAGIC;
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assign fhva[3] = SA_MAGIC;
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assign fhma[FIFO_HK] = 16'h ffff;
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assign fhma[2] = 16'h ffff;
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assign fhma[3] = 16'h ffff;
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assign fsiz[FIFO_HK] = 8*ND;
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assign fsiz[3] = 3*ND + 2;
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thhor_core core
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( .mclk(mclk),
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.we(we), .wp(wp), .wa(wa), .wd(wd), .re(re), .rd(rd),
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.confs(confs), .resets(resets),
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.ax_states(states), .ax_strobes(strobes),
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.fifo_e({fifo_push[3:2], fifo_push[FIFO_HK]}),
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.fifo1(fifo[FIFO_HK]), .fifo2(fifo[2]), .fifo3(fifo[3]),
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.afull({fifo_full[3:2], fifo_full[FIFO_HK]}),
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.ev_psize(fsiz[2]),
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.counter_hit(counter_hit), .stick(stick), .clock(clock),
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.SCLK(ADC_SCK), .nCS(ADC_nCS), .DIN(ADC_DIN), .DOUT(ADC_DOUT) );
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endmodule // thhor_crs
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`ifdef SIMULATION
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`timescale 1ns/1ps
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`ifdef THHOR_CRS_TEST
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module thhor_crs_test;
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wire sclk, mosi, miso;
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ssp_test spi(.sclk(sclk), .mosi(mosi), .miso(miso));
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wire xclk;
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wire [3:0] SCLK, nCS, DIN, DOUT;
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stis_ana_jig #(.SLICES(1), .ND(4)) jig
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( .xclk(xclk), .SCLK(SCLK[0]), .nCS(nCS[0]), .DIN(DIN[0]), .DOUT(DOUT));
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always @(jig.send_command)
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begin
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if (jig.awp)
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spi.cmdp(jig.awa, jig.awd);
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else
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spi.cmd(jig.awa);
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-> jig.end_command;
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end
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wire pt_MCLK, pt_SCLK, pt_Din, pt_Dout;
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ms5540c_sim bate(pt_MCLK, pt_SCLK, pt_Din, pt_Dout);
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thhor_crs dut
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(
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.xclk(xclk),
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.S_IN(1'b0),
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.spi_ssel(1'b1), .spi_sck(sclk), .spi_mosi(mosi), .spi_miso(miso),
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.pt_MCLK(pt_MCLK), .pt_SCLK(pt_SCLK), .pt_Din(pt_Din), .pt_Dout(pt_Dout),
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.ADC_SCK(SCLK), .ADC_nCS(nCS), .ADC_DIN(DIN), .ADC_DOUT(DOUT)
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);
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initial
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begin
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$dumpfile("vcd/thhor_crs.fst");
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$dumpvars(0);
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#100 spi.verbose <= 2;
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#100 spi.frame(0);
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#4_000; // force a frame timeout
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#100 spi.frame(0);
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spi.rx_idle = 16'h 0000;
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spi.cmdp(dut.front.SPIDE_ADDR, spi.rx_idle);
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spi.cmdp(dut.front.HKSZ_ADDR, 0);
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spi.cmd(dut.front.MRSTS_ADDR);
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spi.cmdp(dut.front.MCONF_ADDR+3, 16'b 0000_1000_1111_1000);
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spi.cmdp(dut.core.MISC_ADDR+11, 16'b 0000_0001_0000_1000);
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spi.cmdp(dut.front.MRSTS_ADDR, 16'b 0000_0001_1111_1100);
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jig.l1_conf;
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jig.l2_conf;
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jig.l3_conf;
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spi.cmdp(dut.core.DORN_ADDR+'h8, 16'h 0e0e);
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spi.cmdp(dut.core.DORN_ADDR+'h9, 16'h 000e);
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spi.cmdp(dut.core.DORN_ADDR+'ha, 16'h 0000);
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spi.cmdp(dut.core.DORN_ADDR+'hb, {8'b 01, 8'd 16});
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spi.cmdp(dut.front. MCONF_ADDR+2, 16'b 0000_0000_0000_0001);
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#30000;
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jig.pulse(0,0,1);
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jig.pulse(0, 'b 00_01, 0);
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#20000 jig.pulse(0, 'b 01_11, 0);
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#4000 jig.pulse(0, 'b 10_10, 0);
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#50000 jig.pulse(0, 'b 00_01, 3);
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#1000 jig.pulse(0, 'b 01_11, 1);
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#20000 jig.pulse(0, 'b 10_10, 1);
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repeat(100) spi.cmd(0);
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spi.cmd(dut.CNTR_ADDR + 'b 1111);
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repeat(100) spi.cmd(0);
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spi.cmd(dut.BATE_ADDR + 'b 0111_1111);
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repeat(1000) spi.cmd(0);
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spi.cmdp(dut.core.MISC_ADDR+11, 16'b 0000_0000_0001_0000);
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repeat(2000) spi.cmd(0);
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#10000 $finish();
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end
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endmodule
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`endif
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`endif
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