turbo_weather/turbo.sch

v 20220529 2
C 40000 40000 0 0 0 title-B.sym
{
T 50200 41100 5 10 1 1 0 0 1
title=Turbo the Turtle's Dosimeter
T 54200 40100 5 10 1 1 0 0 1
author=Stephan I. Böttcher
T 50200 40400 5 10 1 1 0 0 1
file=turbo.sch
T 50200 40800 5 10 1 1 0 0 1
url=https://codeberg.org/SiB64/turbo_weather
}
C 54100 41600 1 0 0 board.sym
{
T 55425 42200 5 10 1 1 0 4 1
footprint=gseboard
T 55400 42675 5 10 1 1 0 4 1
refdes=BOARD
T 55400 42450 5 10 1 1 0 4 1
value=turbo_dose
T 55400 42025 5 5 1 0 0 4 1
net=GND:1
}
C 42300 46200 1 0 0 header4.sym
{
T 42800 47500 5 10 1 1 0 6 1
device=MOSFET
T 42200 46350 5 10 1 1 0 4 1
refdes=U3
T 42900 46100 5 10 1 1 0 6 1
footprint=SIL_100_4
T 42200 47500 5 10 0 1 0 6 1
value=SIL4
}
C 45100 46800 1 0 0 ATtiny404.sym
{
T 47000 49050 5 10 1 1 0 6 1
refdes=U1
T 45400 49250 5 10 0 0 0 0 1
device=ATtiny404
T 46200 46800 5 7 1 1 0 4 1
footprint=SOIC_150_14
T 45100 46800 5 10 0 1 0 0 1
value=ATtiny4x4SS
}
C 43000 47200 1 90 0 gnd-1.sym
C 52900 47100 1 90 0 generic-power.sym
{
T 52650 47300 5 10 0 1 90 3 1
net=Vbat:1
T 52675 47300 5 7 1 1 90 3 1
documentation=Vbat
}
C 53400 45800 1 0 0 LT1761ES5-SD.sym
{
T 54900 47400 5 10 0 1 0 0 1
device=LT1761ES5-BYP
T 54300 47100 5 10 1 1 0 4 1
refdes=U5
T 54800 46100 5 5 1 1 0 8 1
footprint=SOT23_5
T 52700 45800 5 10 1 1 0 0 1
value=LT1761-SD / -BYP
}
C 54200 45200 1 0 0 gnd-1.sym
C 51800 44900 1 270 0 battery-1.sym
{
T 52700 44600 5 10 0 0 270 0 1
device=BATTERY
T 52200 44600 5 10 1 1 0 0 1
refdes=B1
T 53100 44600 5 10 0 0 270 0 1
symversion=0.2
T 52200 44400 5 10 1 1 0 0 1
value=6V
T 51700 44600 5 10 1 1 90 3 1
footprint=KEYSTONE-1025-7
}
C 55700 46400 1 90 0 resistor-2.sym
{
T 55350 46800 5 10 0 0 90 0 1
device=RESISTOR
T 55700 46850 5 10 1 1 90 5 1
refdes=R3
T 55200 46600 5 10 0 1 90 0 1
footprint=C0603.fp
T 55450 46850 5 10 1 1 90 3 1
value=3.3MΩ
T 55000 46600 5 10 0 0 90 0 1
symversion=0.1
}
N 55800 47300 55100 47300 4
N 55100 46400 55600 46400 4
{
T 55000 46450 5 5 1 1 0 0 1
netname=ADJ_CC
}
C 55700 45500 1 90 0 resistor-2.sym
{
T 55350 45900 5 10 0 0 90 0 1
device=RESISTOR
T 55700 45950 5 10 1 1 90 5 1
refdes=R4
T 55200 45700 5 10 0 1 90 0 1
footprint=C0603.fp
T 55450 45950 5 10 1 1 90 3 1
value=2.2MΩ
T 55000 45700 5 10 0 0 90 0 1
symversion=0.1
}
C 55500 45200 1 0 0 gnd-1.sym
N 54300 45500 54300 45800 4
C 51800 45000 1 0 0 generic-power.sym
{
T 52000 45250 5 10 0 1 0 3 1
net=Vbat:1
T 52000 45225 5 7 1 1 0 3 1
documentation=Vbat
}
C 51900 43800 1 0 0 gnd-1.sym
C 47600 48700 1 90 0 gnd-1.sym
C 45100 48600 1 90 0 vcc-1.sym
C 55800 47500 1 270 0 vcc-1.sym
N 52900 47300 53500 47300 4
C 53500 46400 1 90 0 resistor-2.sym
{
T 53150 46800 5 10 0 0 90 0 1
device=RESISTOR
T 53400 46850 5 10 1 1 90 4 1
refdes=R13
T 53000 46600 5 10 0 1 90 0 1
footprint=C0603.fp
T 53250 46850 5 10 1 1 90 3 1
value=-SD: 10kΩ
T 52800 46600 5 10 0 0 90 0 1
symversion=0.1
}
N 53500 46400 52900 46400 4
{
T 53400 46350 5 5 1 1 0 5 1
netname=BYP
}
C 52000 46200 1 0 0 capacitor-1.sym
{
T 52200 46900 5 10 0 0 0 0 1
device=CAPACITOR
T 52500 46400 5 10 1 1 0 2 1
refdes=C4
T 52200 47100 5 10 0 0 0 0 1
symversion=0.2
T 52200 46900 5 10 0 1 0 0 1
footprint=C0603
T 52000 46000 5 10 1 1 0 0 1
value=-BYP 100nF
}
C 52000 46200 1 90 0 vcc-1.sym
T 52400 46800 9 7 1 0 0 5 1
(for -BYP option)
C 43700 48300 1 180 1 input-2.sym
{
T 43700 48100 5 10 0 0 180 6 1
net=DRAIN:1
T 44300 47600 5 10 0 0 180 6 1
device=none
T 44350 48200 5 7 1 1 180 7 1
value=DRAIN
}
C 52200 42400 1 90 0 capacitor-1.sym
{
T 51500 42600 5 10 0 0 90 0 1
device=CAPACITOR
T 51650 42800 5 10 1 1 0 2 1
refdes=C11
T 51300 42600 5 10 0 0 90 0 1
symversion=0.2
T 51500 42600 5 10 0 1 90 0 1
footprint=C0603
T 51900 42900 5 10 0 1 90 0 1
value=100nF
}
C 52700 42400 1 90 0 capacitor-1.sym
{
T 52000 42600 5 10 0 0 90 0 1
device=CAPACITOR
T 52450 42550 5 10 1 1 180 2 1
refdes=C12
T 51800 42600 5 10 0 0 90 0 1
symversion=0.2
T 52000 42600 5 10 0 1 90 0 1
footprint=C0603
T 52400 42900 5 10 0 1 90 0 1
value=100nF
}
N 52000 42400 53600 42400 4
N 52000 43300 53600 43300 4
C 51800 43300 1 0 0 vcc-1.sym
C 51900 42100 1 0 0 gnd-1.sym
C 52800 43300 1 270 0 capacitor-4.sym
{
T 53900 43100 5 10 0 0 270 0 1
device=POLARIZED_CAPACITOR
T 52950 42500 5 10 1 1 180 2 1
refdes=C26
T 53500 43100 5 10 0 0 270 0 1
symversion=0.2
T 53500 43100 5 10 0 1 270 0 1
footprint=P1206
T 53100 43100 5 10 0 1 270 0 1
value=10µF
}
C 53400 43300 1 270 0 capacitor-4.sym
{
T 54500 43100 5 10 0 0 270 0 1
device=POLARIZED_CAPACITOR
T 53550 42500 5 10 1 1 180 2 1
refdes=C29
T 54100 43100 5 10 0 0 270 0 1
symversion=0.2
T 54100 43100 5 10 0 1 270 0 1
footprint=P1206
T 53700 43100 5 10 0 1 270 0 1
value=10µF
}
C 43900 49000 1 90 0 led-3.sym
{
T 43250 49950 5 10 0 0 90 0 1
device=LED
T 43350 49550 5 10 1 1 180 0 1
refdes=D1
T 44000 49700 5 10 1 1 180 6 1
footprint=C0603
T 44000 49500 5 10 1 1 180 6 1
value=SMD-LED
}
C 43600 49100 1 270 0 resistor-2.sym
{
T 43950 48700 5 10 0 0 270 0 1
device=RESISTOR
T 43700 48650 5 10 1 1 90 4 1
refdes=R11
T 44100 48900 5 10 0 1 270 0 1
footprint=C0603.fp
T 43500 48650 5 10 1 1 90 4 1
value=10kΩ
T 44300 48900 5 10 0 0 270 0 1
symversion=0.1
}
C 52600 45000 1 270 0 capacitor-4.sym
{
T 53700 44800 5 10 0 0 270 0 1
device=POLARIZED_CAPACITOR
T 53300 44800 5 10 0 0 270 0 1
symversion=0.2
T 53300 44800 5 10 0 1 270 0 1
footprint=P1206
T 52450 44450 5 10 1 1 0 2 1
refdes=C20
T 52600 43900 5 10 0 1 0 0 1
value=10µF
}
N 52800 45000 52000 45000 4
N 52800 44100 52000 44100 4
N 52000 44100 52000 44200 4
N 52000 45000 52000 44900 4
C 41600 41600 1 0 0 DB9-1.sym
{
T 42600 44500 5 10 0 0 0 0 1
device=DB9
T 41800 44800 5 10 1 1 0 0 1
refdes=CONN1
T 41800 41300 5 10 1 1 0 0 1
footprint=SUBD9_PINS
T 41800 41100 5 10 1 1 0 0 1
value=D9 pigtail
}
C 43100 43900 1 90 0 gnd-1.sym
C 43100 42700 1 90 0 gnd-1.sym
C 42800 42100 1 270 0 generic-power.sym
{
T 43050 41900 5 10 0 1 270 3 1
net=Vbat:1
T 43025 41900 5 7 1 1 270 3 1
documentation=Vbat
}
C 43100 42100 1 90 0 gnd-1.sym
C 43600 47200 1 0 0 input-2.sym
{
T 43600 47400 5 10 0 0 0 0 1
net=RxD:1
T 44200 47900 5 10 0 0 0 0 1
device=none
T 44250 47300 5 7 1 1 0 1 1
value=RxD
}
N 45000 47300 45100 47300 4
C 44200 42600 1 180 0 input-2.sym
{
T 44200 42400 5 10 0 0 180 0 1
net=RxD:1
T 43600 41900 5 10 0 0 180 0 1
device=none
T 43550 42500 5 7 1 1 180 1 1
value=RxD
}
C 44200 43200 1 180 0 input-2.sym
{
T 44200 43000 5 10 0 0 180 0 1
net=TxD:1
T 43600 42500 5 10 0 0 180 0 1
device=none
T 43550 43100 5 7 1 1 180 1 1
value=TxD
}
C 48700 47700 1 180 0 input-2.sym
{
T 48700 47500 5 10 0 0 180 0 1
net=Reset:1
T 48100 47000 5 10 0 0 180 0 1
device=none
T 48050 47600 5 7 1 1 180 1 1
value=Reset
}
C 44200 43800 1 180 0 input-2.sym
{
T 44200 43600 5 10 0 0 180 0 1
net=Reset:1
T 43600 43100 5 10 0 0 180 0 1
device=none
T 43550 43700 5 7 1 1 180 1 1
value=Reset
}
C 43100 43300 1 90 0 gnd-1.sym
C 44800 41600 1 90 0 input-2.sym
{
T 44600 41600 5 10 0 0 90 0 1
net=Reset:1
T 44100 42200 5 10 0 0 90 0 1
device=none
T 44700 42250 5 7 1 1 90 1 1
value=Reset
}
C 44300 42600 1 0 0 gnd-1.sym
C 43700 48400 1 0 0 input-2.sym
{
T 43700 48600 5 10 0 0 0 0 1
net=SSEL:1
T 44300 49100 5 10 0 0 0 0 1
device=none
T 44350 48500 5 7 1 1 0 1 1
value=SSEL
}
N 42600 47300 42700 47300 4
N 44700 42900 44700 43400 4
C 44500 44200 1 0 0 vcc-1.sym
N 44700 44200 44700 44300 4
C 44600 44300 1 270 0 resistor-2.sym
{
T 44950 43900 5 10 0 0 270 0 1
device=RESISTOR
T 44700 43850 5 10 1 1 90 4 1
refdes=R12
T 45100 44100 5 10 0 1 270 0 1
footprint=C0603.fp
T 44900 43850 5 10 1 1 90 4 1
value=∞Ω
T 45300 44100 5 10 0 2 270 0 1
symversion=0.1
T 44550 43850 5 5 1 1 90 3 1
note=not needed
}
N 43700 49000 43700 49100 4
{
T 43650 49000 5 5 1 1 90 0 1
netname=LEDR
}
C 48700 46900 1 0 1 input-2.sym
{
T 48700 47100 5 10 0 0 0 6 1
net=AIN2:1
T 48100 47600 5 10 0 0 0 6 1
device=none
T 48050 47000 5 7 1 1 0 7 1
value=AIN2
}
T 52900 46900 9 7 1 0 90 5 1
(for -SD option)
C 43600 46900 1 0 0 input-2.sym
{
T 43600 47100 5 10 0 0 0 0 1
net=TxD:1
T 44200 47600 5 10 0 0 0 0 1
device=none
T 44250 47000 5 7 1 1 0 1 1
value=TxD
}
N 45000 47000 45100 47000 4
T 52300 41600 9 10 1 0 0 0 2
C26…C27, 1206
use 10µF 25V X7R
T 50850 41600 9 10 1 0 0 0 2
C11…C12, 0603
use 100nF X7R
T 46750 40450 9 10 1 0 0 0 1
All R are size 0603
T 44950 49500 9 10 1 0 0 0 5
• SPI for SCK, MISO, MOSI
• Timer PWM output for MCLK
• UART TxD for output
• UART RxD (optional) for configuration
• Any  IO for RF_EN
T 43800 41350 9 10 1 0 0 0 3
UPDI (Unified Program 
and Debug Interface)
via J1 or CONN1
C 44000 43100 1 270 0 header3.sym
{
T 45200 43000 5 10 0 0 270 0 1
device=CONNECTOR_3
T 44400 43350 5 10 1 1 0 4 1
refdes=J1
T 44900 42900 5 10 0 1 0 0 1
footprint=SIL_100_3
T 44900 43100 5 10 0 1 0 0 1
value=HE_100_1×3
}
C 44300 42900 1 180 0 vcc-1.sym
L 55300 46300 55000 46300 3 10 1 0 -1 -1
L 55000 46300 55075 46325 3 10 1 0 -1 -1
L 55000 46300 55075 46275 3 10 1 0 -1 -1
T 55200 46300 9 5 1 0 0 5 1
30nA
T 54400 43800 9 10 1 0 0 0 5
Vcc  = 1.22V × (1+R₃/R₄) 
            + 30nA × R₃
Vcc  = 3.15V
Vrf  = 3.06V
I_R₃ = 0.6 µA
C 53800 47900 1 0 0 resistor-2.sym
{
T 54200 48250 5 10 0 0 0 0 1
device=RESISTOR
T 54250 48000 5 10 1 1 0 4 1
refdes=R10
T 54000 48400 5 10 0 1 0 0 1
footprint=C0603.fp
T 54250 48150 5 10 1 1 0 3 1
value=∞Ω/0Ω
T 54000 48600 5 10 0 0 0 0 1
symversion=0.1
}
N 53400 47300 53400 48000 4
N 53400 48000 53800 48000 4
N 54700 48000 55600 48000 4
N 55600 48000 55600 47300 4
C 43500 49700 1 0 0 vcc-1.sym
C 43800 46900 1 90 0 input-2.sym
{
T 43600 46900 5 10 0 0 90 0 1
net=TxD:1
T 43100 47500 5 10 0 0 90 0 1
device=none
T 43700 47550 5 7 1 1 90 1 1
value=TxD
}
N 43700 48300 43700 48200 4
N 43700 49700 43700 49900 4
C 48700 48400 1 0 1 input-2.sym
{
T 48700 48600 5 10 0 0 0 6 1
net=SCK:1
T 48100 49100 5 10 0 0 0 6 1
device=none
T 48050 48500 5 7 1 1 0 7 1
value=SCK
}
C 48700 48100 1 0 1 input-2.sym
{
T 48700 48300 5 10 0 0 0 6 1
net=MISO:1
T 48100 48800 5 10 0 0 0 6 1
device=none
T 48050 48200 5 7 1 1 0 7 1
value=MISO
}
C 48700 47800 1 0 1 input-2.sym
{
T 48700 48000 5 10 0 0 0 6 1
net=MOSI:1
T 48100 48500 5 10 0 0 0 6 1
device=none
T 48050 47900 5 7 1 1 0 7 1
value=MOSI
}
C 48700 47200 1 0 1 input-2.sym
{
T 48700 47400 5 10 0 0 0 6 1
net=PWM:1
T 48100 47900 5 10 0 0 0 6 1
device=none
T 48050 47300 5 7 1 1 0 7 1
value=PWM
}
C 43700 47500 1 0 0 input-2.sym
{
T 43700 47700 5 10 0 0 0 0 1
net=AIN1:1
T 44300 48200 5 10 0 0 0 0 1
device=none
T 44350 47600 5 7 1 1 0 1 1
value=AIN1
}
C 44000 46900 1 0 1 input-2.sym
{
T 44000 47100 5 10 0 0 0 6 1
net=GATE2:1
T 43400 47600 5 10 0 0 0 6 1
device=none
T 43350 47000 5 7 1 1 0 7 1
value=GATE2
}
C 48900 41400 1 0 0 gnd-1.sym
C 46600 42500 1 0 0 resistor-2.sym
{
T 47000 42850 5 10 0 0 0 0 1
device=RESISTOR
T 47050 42600 5 10 1 1 0 4 1
refdes=R30
T 46800 43000 5 10 0 1 0 0 1
footprint=C0603.fp
T 47050 42750 5 10 1 1 0 3 1
value=100kΩ
T 46800 43200 5 10 0 0 0 0 1
symversion=0.1
}
C 45300 42500 1 0 0 input-2.sym
{
T 45300 42700 5 10 0 0 0 0 1
net=PWM:1
T 45900 43200 5 10 0 0 0 0 1
device=none
T 45950 42600 5 7 1 1 0 1 1
value=PWM
}
C 47300 42600 1 270 0 capacitor-4.sym
{
T 48400 42400 5 10 0 0 270 0 1
device=POLARIZED_CAPACITOR
T 47450 41800 5 10 1 1 180 2 1
refdes=C31
T 48000 42400 5 10 0 0 270 0 1
symversion=0.2
T 48000 42400 5 10 0 1 270 0 1
footprint=P1206
T 47600 42400 5 10 0 1 270 0 1
value=10µF
}
C 47400 41400 1 0 0 gnd-1.sym
C 47500 42500 1 0 0 resistor-2.sym
{
T 47900 42850 5 10 0 0 0 0 1
device=RESISTOR
T 47950 42600 5 10 1 1 0 4 1
refdes=R32
T 47700 43000 5 10 0 1 0 0 1
footprint=C0603.fp
T 47950 42750 5 10 1 1 0 3 1
value=100kΩ
T 47700 43200 5 10 0 0 0 0 1
symversion=0.1
}
C 48600 41700 1 90 0 capacitor-1.sym
{
T 47900 41900 5 10 0 0 90 0 1
device=CAPACITOR
T 48050 42100 5 10 1 1 0 2 1
refdes=C32
T 47700 41900 5 10 0 0 90 0 1
symversion=0.2
T 47900 41900 5 10 0 1 90 0 1
footprint=C0603
T 48300 42200 5 10 0 1 90 0 1
value=100nF
}
C 48300 41400 1 0 0 gnd-1.sym
N 49000 41700 49000 42400 4
C 49100 43200 1 90 0 resistor-2.sym
{
T 48750 43600 5 10 0 0 90 0 1
device=RESISTOR
T 49000 43650 5 10 1 1 90 4 1
refdes=R34
T 48600 43400 5 10 0 1 90 0 1
footprint=C0603.fp
T 48850 43650 5 10 1 1 90 3 1
value=100kΩ
T 48400 43400 5 10 0 0 90 0 1
symversion=0.1
}
C 49100 45400 1 90 1 input-2.sym
{
T 48900 45400 5 10 0 0 90 6 1
net=DRAIN:1
T 48400 44800 5 10 0 0 90 6 1
device=none
T 49000 44750 5 7 1 1 90 7 1
value=DRAIN
}
C 51600 43100 1 0 1 input-2.sym
{
T 51600 43300 5 10 0 0 0 6 1
net=AIN1:1
T 51000 43800 5 10 0 0 0 6 1
device=none
T 50950 43200 5 7 1 1 0 7 1
value=AIN1
}
N 49000 44000 49000 44100 4
C 47600 44400 1 90 1 input-2.sym
{
T 47400 44400 5 10 0 0 90 6 1
net=GATE:1
T 46900 43800 5 10 0 0 90 6 1
device=none
T 47500 43750 5 7 1 1 90 7 1
value=GATE
}
N 47500 42600 47500 43000 4
N 48400 42600 48500 42600 4
{
T 48650 42650 5 5 1 1 0 6 1
netname=GATE1
}
C 47900 44800 1 0 0 nmos-ub.sym
{
T 48500 45700 5 10 0 0 0 0 1
device=NMOS_TRANSISTOR
T 48500 45400 5 10 1 1 0 0 1
refdes=Q2
T 48500 45200 5 10 1 1 0 0 1
footprint=SOT23_3
T 48500 45000 5 10 1 1 0 0 1
value=2N7002
}
C 48300 44600 1 0 0 gnd-1.sym
C 48000 44100 1 90 0 capacitor-1.sym
{
T 47300 44300 5 10 0 0 90 0 1
device=CAPACITOR
T 47100 44300 5 10 0 0 90 0 1
symversion=0.2
T 47300 44300 5 10 0 1 90 0 1
footprint=C0603
T 47700 44600 5 10 0 1 90 0 1
value=100nF
T 47450 44500 5 10 1 1 0 2 1
refdes=C30
}
C 47700 44000 1 0 0 gnd-1.sym
N 48400 44900 48400 44800 4
C 48500 45600 1 90 0 resistor-2.sym
{
T 48150 46000 5 10 0 0 90 0 1
device=RESISTOR
T 48000 45800 5 10 0 1 90 0 1
footprint=C0603.fp
T 47800 45800 5 10 0 0 90 0 1
symversion=0.1
T 48400 46050 5 10 1 1 90 4 1
refdes=R33
T 48250 46050 5 10 1 1 90 3 1
value=100kΩ
}
C 48500 47800 1 90 1 input-2.sym
{
T 48300 47800 5 10 0 0 90 6 1
net=DRAIN:1
T 47800 47200 5 10 0 0 90 6 1
device=none
T 48400 47150 5 7 1 1 90 7 1
value=DRAIN
}
N 48400 46400 48400 46500 4
N 47800 45000 47900 45000 4
C 46900 44900 1 0 0 resistor-2.sym
{
T 47350 45000 5 10 1 1 0 4 1
refdes=R31
T 47300 45250 5 10 0 0 0 0 1
device=RESISTOR
T 47100 45400 5 10 0 1 0 0 1
footprint=C0603.fp
T 47350 45150 5 10 1 1 0 3 1
value=100kΩ
T 47100 45600 5 10 0 0 0 0 1
symversion=0.1
}
C 51100 45500 1 0 1 input-2.sym
{
T 51100 45700 5 10 0 0 0 6 1
net=AIN2:1
T 50500 46200 5 10 0 0 0 6 1
device=none
T 50450 45600 5 7 1 1 0 7 1
value=AIN2
}
C 45600 45100 1 180 1 input-2.sym
{
T 45600 44900 5 10 0 0 180 6 1
net=GATE:1
T 46200 44400 5 10 0 0 180 6 1
device=none
T 46250 45000 5 7 1 1 180 7 1
value=GATE
}
N 47000 45000 46900 45000 4
N 46700 42600 46600 42600 4
C 44000 46600 1 0 1 input-2.sym
{
T 44000 46800 5 10 0 0 0 6 1
net=DRAIN2:1
T 43400 47300 5 10 0 0 0 6 1
device=none
T 43350 46700 5 7 1 1 0 7 1
value=DRAIN2
}
C 47900 46800 1 90 1 input-2.sym
{
T 47700 46800 5 10 0 0 90 6 1
net=GATE2:1
T 47200 46200 5 10 0 0 90 6 1
device=none
T 47800 46150 5 7 1 1 90 7 1
value=GATE2
}
N 47800 45000 47800 45400 4
T 54150 48900 9 10 1 0 0 0 3
To use Vbat directly:
R10=0Ω 
U5 unpopulated.
C 49500 47400 1 0 0 AT45DB081D-1.sym
{
T 50500 49000 5 10 1 1 0 4 1
refdes=U2
T 49800 50350 5 10 0 1 0 0 1
device=AT45DB081D
T 50500 48400 5 10 1 1 0 4 1
footprint=SOIC_150_8
T 49800 51600 5 10 0 0 0 0 1
symversion=1.0
T 50500 48750 5 10 1 1 0 4 1
value=AT45DB161E
}
C 48300 48800 1 0 0 input-2.sym
{
T 48300 49000 5 10 0 0 0 0 1
net=MOSI:1
T 48900 49500 5 10 0 0 0 0 1
device=none
T 48950 48900 5 7 1 1 0 1 1
value=MOSI
}
C 52700 48800 1 0 1 input-2.sym
{
T 52700 49000 5 10 0 0 0 6 1
net=MISO:1
T 52100 49500 5 10 0 0 0 6 1
device=none
T 52050 48900 5 7 1 1 0 7 1
value=MISO
}
C 48300 48400 1 0 0 input-2.sym
{
T 48300 48600 5 10 0 0 0 0 1
net=SCK:1
T 48900 49100 5 10 0 0 0 0 1
device=none
T 48950 48500 5 7 1 1 0 1 1
value=SCK
}
C 52700 49200 1 0 1 input-2.sym
{
T 52700 49400 5 10 0 0 0 6 1
net=SSEL:1
T 52100 49900 5 10 0 0 0 6 1
device=none
T 52050 49300 5 7 1 1 0 7 1
value=SSEL
}
C 50400 49800 1 0 0 vcc-1.sym
C 49700 47900 1 90 0 vcc-1.sym
C 49700 49100 1 90 0 vcc-1.sym
C 50500 47300 1 0 0 gnd-1.sym
N 50600 47600 50600 47400 4
N 50600 49800 50600 50000 4
N 51300 49300 51500 49300 4
N 51300 48900 51500 48900 4
N 49700 49300 49500 49300 4
N 49700 48100 49500 48100 4
N 49700 48500 49500 48500 4
N 49700 48900 49500 48900 4
C 44000 46300 1 0 1 input-2.sym
{
T 44000 46500 5 10 0 0 0 6 1
net=DRAIN:1
T 43400 47000 5 10 0 0 0 6 1
device=none
T 43350 46400 5 7 1 1 0 7 1
value=DRAIN
}
C 48800 45500 1 0 0 resistor-2.sym
{
T 49250 45600 5 10 1 1 0 4 1
refdes=R35
T 49200 45850 5 10 0 0 0 0 1
device=RESISTOR
T 49000 46000 5 10 0 1 0 0 1
footprint=C0603.fp
T 49250 45750 5 10 1 1 0 3 1
value=100kΩ
T 49000 46200 5 10 0 0 0 0 1
symversion=0.1
}
N 48400 45600 48800 45600 4
C 48900 47000 1 90 1 input-2.sym
{
T 48700 47000 5 10 0 0 90 6 1
net=DRAIN2:1
T 48200 46400 5 10 0 0 90 6 1
device=none
T 48800 46350 5 7 1 1 90 7 1
value=DRAIN2
}
C 49900 44700 1 90 0 capacitor-1.sym
{
T 49200 44900 5 10 0 0 90 0 1
device=CAPACITOR
T 49000 44900 5 10 0 0 90 0 1
symversion=0.2
T 49200 44900 5 10 0 1 90 0 1
footprint=C0603
T 49600 45200 5 10 0 1 90 0 1
value=100nF
T 49350 45100 5 10 1 1 0 2 1
refdes=C33
}
C 49600 44600 1 0 0 gnd-1.sym
N 49700 44900 49700 44700 4
N 47800 44300 47800 44100 4
C 49300 43100 1 0 0 resistor-2.sym
{
T 49750 43200 5 10 1 1 0 4 1
refdes=R36
T 49700 43450 5 10 0 0 0 0 1
device=RESISTOR
T 49500 43600 5 10 0 1 0 0 1
footprint=C0603.fp
T 49750 43350 5 10 1 1 0 3 1
value=100kΩ
T 49500 43800 5 10 0 0 0 0 1
symversion=0.1
}
C 50400 42300 1 90 0 capacitor-1.sym
{
T 49700 42500 5 10 0 0 90 0 1
device=CAPACITOR
T 49500 42500 5 10 0 0 90 0 1
symversion=0.2
T 49700 42500 5 10 0 1 90 0 1
footprint=C0603
T 50100 42800 5 10 0 1 90 0 1
value=100nF
T 49850 42700 5 10 1 1 0 2 1
refdes=C34
}
C 50100 42200 1 0 0 gnd-1.sym
N 50200 42500 50200 42300 4
N 49000 43200 49300 43200 4
{
T 49400 43250 5 5 1 1 0 6 1
netname=DRAIN1
}
C 48500 42400 1 0 0 nmos-ub.sym
{
T 49100 43300 5 10 0 0 0 0 1
device=NMOS_TRANSISTOR
T 49100 43000 5 10 1 1 0 0 1
refdes=Q1
T 49100 42800 5 10 1 1 0 0 1
footprint=SOT23_3
T 49100 42600 5 10 1 1 0 0 1
value=2N7002
}
C 43700 48000 1 180 1 input-2.sym
{
T 43700 47800 5 10 0 0 180 6 1
net=GATE:1
T 44300 47300 5 10 0 0 180 6 1
device=none
T 44350 47900 5 7 1 1 180 7 1
value=GATE
}