solo_altera/adc/altera/Makefile

VERILOG=/usr/local/bin/iverilog
#VERILOG=/usr/bin/iverilog

VERILOGFLAGS = -v -DSIMULATION $($*_FLAGS)
%.vvp: %.v
	$(VERILOG) $(VERILOGFLAGS) -o $@ $^

vcd/%.lxt: %.vvp
	$< -lxt2 | tee $*.log

.PRECIOUS: vcd/%.lxt vcd/%.vcd

VPATH=.:../../altera:../../altera/mega:../../irena/altera/adc128

QUARTUS=/usr/local/quartus/altera9.1sp1/quartus
export PATH:=$(PATH):$(QUARTUS)/bin

%.rbf: %.qpf %.qsf %.sdc %.v 
	quartus_map $<
	quartus_fit $<
	quartus_asm $<
	quartus_sta $<
	grep -i warning $*.*.rpt | grep -v 'truncated value with size 32 ' > $*.warnings

adctest.rbf: conf_reg.v spififo.v \
       secondcyclone.v  pll240d.vhd serializer.v \
       sfilter.v

adctest.vvp: conf_reg.v spififo.v secondcyclone.v \
    pll240d.vhd serializer.v \
    sfilter.v

rhf1401_FLAGS = -DRFH1401_TEST