6f40a696a7
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@952 bc5caf13-1734-44f8-af43-603852e9ee25
34 lines
788 B
Makefile
34 lines
788 B
Makefile
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VERILOG=/usr/local/bin/iverilog
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#VERILOG=/usr/bin/iverilog
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VERILOGFLAGS = -v -DSIMULATION $($*_FLAGS)
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%.vvp: %.v
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$(VERILOG) $(VERILOGFLAGS) -o $@ $^
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vcd/%.lxt: %.vvp
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$< -lxt2 | tee $*.log
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.PRECIOUS: vcd/%.lxt vcd/%.vcd
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VPATH=.:../../altera:../../altera/mega:../../irena/altera/adc128
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QUARTUS=/usr/local/quartus/altera9.1sp1/quartus
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export PATH:=$(PATH):$(QUARTUS)/bin
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%.rbf: %.qpf %.qsf %.sdc %.v
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quartus_map $<
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quartus_fit $<
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quartus_asm $<
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quartus_sta $<
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grep -i warning $*.*.rpt | grep -v 'truncated value with size 32 ' > $*.warnings
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adctest.rbf: conf_reg.v spififo.v \
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secondcyclone.v pll240d.vhd serializer.v \
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sfilter.v
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adctest.vvp: conf_reg.v spififo.v secondcyclone.v \
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pll240d.vhd serializer.v \
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sfilter.v
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rhf1401_FLAGS = -DRFH1401_TEST
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