40 lines
1.1 KiB
Makefile
40 lines
1.1 KiB
Makefile
|
|
||
|
|
VERILOG=/usr/local/bin/iverilog
|
||
|
|
#VERILOG=/usr/bin/iverilog
|
||
|
|
|
||
|
|
VERILOGFLAGS = -v -Wall -Wno-timescale -DSIMULATION $($*_FLAGS)
|
||
|
|
%.vvp: %.v
|
||
|
|
-grep TODO $(filter %.v,$^) > TODO.$*
|
||
|
|
$(VERILOG) $(VERILOGFLAGS) -o $@ $(filter %.v,$^)
|
||
|
|
|
||
|
|
vcd/%.lxt: %.vvp
|
||
|
|
$< -lxt2 | tee $*.log
|
||
|
|
|
||
|
|
.PRECIOUS: vcd/%.lxt
|
||
|
|
|
||
|
|
VPATH=../../altera:../../altera/mega:../../hetept/altera:\
|
||
|
|
../../irena/altera/adc128:../../irena/altera/direna:\
|
||
|
|
../../sirena/altera
|
||
|
|
|
||
|
|
rpirena_FLAGS = -srpirena_test -DRPIRENA_TEST -DNOHALFCLK -DWITH_SPI_SSEL -DHAVE_ABT2F
|
||
|
|
rpirena.vvp: rpirena.v \
|
||
|
|
frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v \
|
||
|
|
frontend_test.v fifo8_sim.v hkadc.v adc128s102.v pulser.v \
|
||
|
|
filter.v sfilter.v irena_core.v adccntl.v itof.v \
|
||
|
|
direna_test.v
|
||
|
|
|
||
|
|
QUARTUS=/usr/local/quartus/altera9.1sp1/quartus
|
||
|
|
export PATH:=$(PATH):$(QUARTUS)/bin
|
||
|
|
|
||
|
|
%.rbf: %.qpf %.qsf %.sdc %.v
|
||
|
|
quartus_map $<
|
||
|
|
quartus_fit $<
|
||
|
|
quartus_asm $<
|
||
|
|
quartus_sta $<
|
||
|
|
grep -i warning $*.*.rpt > $*.warnings
|
||
|
|
|
||
|
|
FRONTEND = conf_reg.v spi_slave.v pll96.v spififo.v frontend.v packetfifo.v
|
||
|
|
HKADC = hkadc.v adc128s102.v
|
||
|
|
IRENA = filter.v sfilter.v irena_core.v adccntl.v itof.v
|
||
|
|
|
||
|
|
rpirena.rbf: $(FRONTEND) $(HKADC) $(IRENA)
|