9b1e605578
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2456 bc5caf13-1734-44f8-af43-603852e9ee25
40 lines
1.1 KiB
Makefile
40 lines
1.1 KiB
Makefile
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VERILOG=/usr/local/bin/iverilog
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#VERILOG=/usr/bin/iverilog
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VERILOGFLAGS = -v -Wall -Wno-timescale -DSIMULATION $($*_FLAGS)
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%.vvp: %.v
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-grep TODO $(filter %.v,$^) > TODO.$*
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$(VERILOG) $(VERILOGFLAGS) -o $@ $(filter %.v,$^)
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vcd/%.lxt: %.vvp
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$< -lxt2 | tee $*.log
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.PRECIOUS: vcd/%.lxt
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VPATH=../../altera:../../altera/mega:../../hetept/altera:\
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../../irena/altera/adc128:../../irena/altera/direna:\
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../../sirena/altera
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rpirena_FLAGS = -srpirena_test -DRPIRENA_TEST -DNOHALFCLK -DWITH_SPI_SSEL -DHAVE_ABT2F
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rpirena.vvp: rpirena.v \
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frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v \
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frontend_test.v fifo8_sim.v hkadc.v adc128s102.v pulser.v \
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filter.v sfilter.v irena_core.v adccntl.v itof.v \
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direna_test.v
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QUARTUS=/usr/local/quartus/altera9.1sp1/quartus
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export PATH:=$(PATH):$(QUARTUS)/bin
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%.rbf: %.qpf %.qsf %.sdc %.v
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quartus_map $<
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quartus_fit $<
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quartus_asm $<
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quartus_sta $<
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grep -i warning $*.*.rpt > $*.warnings
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FRONTEND = conf_reg.v spi_slave.v pll96.v spififo.v frontend.v packetfifo.v
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HKADC = hkadc.v adc128s102.v
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IRENA = filter.v sfilter.v irena_core.v adccntl.v itof.v
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rpirena.rbf: $(FRONTEND) $(HKADC) $(IRENA)
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