solo_altera/flyrena/altera/Makefile

VERILOG=/usr/local/bin/iverilog
VVP=$(subst iverilog,vvp,$(VERILOG))
#VERILOG=/usr/bin/iverilog

VERILOGFLAGS = -v -Wall -Wno-timescale -DSIMULATION $($*_FLAGS)
%.vvp: %.v
	grep TODO $(filter %.v,$^) > TODO.$*
	$(VERILOG) $(VERILOGFLAGS) -o $@ $(filter %.v,$^)

vcd/%.lxt: %.vvp
	$(VVP) -v $< -lxt2 | tee $*.log

.PRECIOUS: vcd/%.lxt

VPATH=../../arena/altera:../../areana/altera/adc128:\
../../irena/altera/adc128:../../hetept/altera:\
../../sirena/altera:../../sirena/altera/l3:../../sirena/altera/encode:\
../../altera:../../altera/mega:../../altera/actel

flyrena_RAM = -DINFERRED_SRAM
flyrena_FLAGS = -DFLYRENA_TEST -DHETEPTANA_TEST -DUART3MHZ -DGENSRAM $(flyrena_RAM)  -s flyrena_test

flyrena.vvp:  flyrena.v secondcyclone.v serializer.v \
 countbits.v actel.v \
 frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v \
 ad9649.v frontend_test.v  fifo8_sim.v \
 adc_data.v oscilloscope.v spi_master_adc.v \
 icucore.v \
 heteptana.v sfilter.v adc128s102.v hkadc.v pulser.v \
 heteptcore.v backend.v opheater.v por.v \
 message.v uart.v crc.v \
 msg_regs.v ppsschedule.v l3code.v hamming.v \
 pulse.hex ppsschedule.hex memport.v eeprom.v \
 compression.v encode.v itof.v log2by8.v \
 processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v \
 adderi.v mult.v bitrange.v \
 mem.v l3registerfile.v counters.v fifo.v pha.v

heteptdig_RAM = -DACTEL_SRAM -DSEU_RATE=50
heteptdig_SRAM = -DMEM16EE 
heteptdig_OPTIONS =
heteptdig_FLAGS = -s heteptdig_test $(heteptdig_OPTIONS) \
 -DHETEPTDIG_TEST -DHETEPTANA_TEST \
 -DARxSTREAM \
 -DUART3MHZ -DM24MHZ $(heteptdig_RAM) $(heteptdig_SRAM)

ce4dig_RAM = -DACTEL_SRAM -DSEU_RATE=50
ce4dig_SRAM = -DMEM16EE 
ce4dig_OPTIONS =
ce4dig_FLAGS = -s ce4dig_test $(ce4dig_OPTIONS) \
 -DChangE4 -DREMOTE_ADC -DNO_MSG_TIMEOUT -DUART_PARITY=1 \
 -DCE4DIG_TEST -DHETEPTANA_TEST \
 -DARxSTREAM \
 -DUART3MHZ -DM24MHZ $(ce4dig_RAM) $(ce4dig_SRAM)

HETEPTDIG_SOURCES = secondcyclone.v serializer.v \
 icucore.v \
 heteptana.v sfilter.v adc128s102.v hkadc.v pulser.v \
 heteptcore.v backend.v opheater.v por.v \
 message.v uart.v crc.v \
 msg_regs.v ppsschedule.v l3code.v hamming.v \
 pulse.hex ppsschedule.hex memport.v eeprom.v \
 compression.v encode.v itof.v log2by8.v \
 processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v \
 adderi.v mult.v bitrange.v \
 mem.v l3registerfile.v counters.v fifo.v pha.v	 \
 RAM64K36_sim.v memWxActel.v actel.v \
 mem36x128.v mem36x256.v mem36x512.v mem36x1024.v mem36x2048.v \
 mem72x128.v mem72x256.v mem72x512.v mem72x1024.v mem72x2048.v

heteptdig.vvp: heteptdig.v $(HETEPTDIG_SOURCES)
ce4dig.vvp: ce4dig.v $(HETEPTDIG_SOURCES)

QUARTUS=/usr/local/quartus/altera9.1sp1/quartus
export PATH:=$(PATH):$(QUARTUS)/bin

%.rbf: %.qpf %.qsf %.sdc %.v \
       frontend.v spi_slave.v conf_reg.v packetfifo.v spififo.v
	quartus_map $<
	quartus_fit $<
	quartus_asm $<
	quartus_sta $<
	grep -i warning $*.*.rpt > $*.warnings

FRONTEND = conf_reg.v spi_slave.v pll96.v spififo.v frontend.v packetfifo.v

flyrena.rbf: spi_master_adc.v \
	  $(FRONTEND) icucore.v \
	  backend.v pha.v eeprom.v l3registerfile.v \
	  arena.v adc_data.v oscilloscope.v \
	  secondcyclone.v serializer.v pll240_96.v pll240d_96.v \
	  message.v uart.v crc.v \
	  msg_regs.v ppsschedule.v l3code.v hamming.v  \
 pulse.hex ppsschedule.hex memport.v eeprom.v \
 compression.v encode.v itof.v \
 processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v \
 adderi.v mult.v bitrange.v \
 mem.v l3registerfile.v counters.v fifo.v pha.v

ppsschedule.vvp: l3code.v hamming.v
ppsschedule_FLAGS = -DPPSSCHEDULE_TEST -DINFERRED_SRAM -s ppsschedule_test