Stephan/solo_altera
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solo_altera/flyrena/altera
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stephan 0b415890bb heteptdig gold 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@6635 bc5caf13-1734-44f8-af43-603852e9ee25
2018-02-23 23:28:15 +00:00
..
ce4dig.v merge C'E4 tuning into trunc 2017-03-17 20:56:45 +00:00
ept.l3v flyrena sim advances 2013-07-11 19:51:35 +00:00
flyrena.gold backend...: 2015-03-18 19:41:12 +00:00
flyrena.gtkw t_busy waveforms 2013-08-27 11:00:12 +00:00
flyrena.qpf flyrena altera skeleton 2012-07-16 11:24:16 +00:00
flyrena.qsf flyrena: fix IO_STANDARD assinment 2016-07-25 12:06:38 +00:00
flyrena.sdc run flyrena link at 48 MHz without ser_clk PLLs 2012-08-03 19:16:15 +00:00
flyrena.v flyrena: sim eeprom 2015-03-16 19:46:38 +00:00
flyrena.warnings flyrena: new Altera bitfiles 2015-03-13 11:16:42 +00:00
heteptdig-NO_BCHANNEL.gold heteptana: add verilog config macro NO_BCHANNEL 2014-10-27 07:44:03 +00:00
heteptdig.gold heteptdig gold 2018-02-23 23:28:15 +00:00
heteptdig.gtkw l3registerfile: add .clear command 2015-05-12 20:44:57 +00:00
heteptdig.v l3registerfile: add .clear command 2015-05-12 20:44:57 +00:00
Makefile C'E4 ana/dig simulation 2016-10-04 19:19:08 +00:00
no_het.l3v heteptdig: new nohet.l3 2014-02-26 22:17:44 +00:00