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solo_altera/flyrena/altera/flyrena.warnings
stephan 71af29c2d6 flyrena: new Altera bitfiles 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3939 bc5caf13-1734-44f8-af43-603852e9ee25
2015-03-13 11:16:42 +00:00

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flyrena.asm.rpt:Info: Quartus II Assembler was successful. 0 errors, 0 warnings
flyrena.fit.rpt: 5. I/O Assignment Warnings
flyrena.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
flyrena.fit.rpt:; I/O Assignment Warnings ;
flyrena.fit.rpt:Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.
flyrena.fit.rpt:Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
flyrena.fit.rpt:Warning: Following 10 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
flyrena.fit.rpt: Warning: Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)"
flyrena.fit.rpt: Warning: Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)"
flyrena.fit.rpt: Warning: Pin "adc_clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "adc_clk(n)"
flyrena.fit.rpt: Warning: Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
flyrena.fit.rpt: Warning: Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
flyrena.fit.rpt: Warning: Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
flyrena.fit.rpt: Warning: Pin "ARxC" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARxC(n)"
flyrena.fit.rpt: Warning: Pin "CRx" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "CRx(n)"
flyrena.fit.rpt: Warning: Pin "ARxD" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARxD(n)"
flyrena.fit.rpt: Warning: Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)"
flyrena.fit.rpt:Warning: Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
flyrena.fit.rpt:Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" output port clk[1] feeds output pin "ATxCP~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
flyrena.fit.rpt:Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" output port clk[1] feeds output pin "ATxCN~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
flyrena.fit.rpt:Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
flyrena.fit.rpt:Warning: Following 1 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
flyrena.fit.rpt:Info: Quartus II Fitter was successful. 0 errors, 18 warnings
flyrena.map.rpt:; afull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; empty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; empty3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; empty3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; empty3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; empty3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; empty3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; empty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; empty3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; ggo ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; q ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; error ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; single ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; error ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; single ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; pend ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; busy ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; d ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; w ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
flyrena.map.rpt:; mrb_w ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
flyrena.map.rpt:; fe_single ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
flyrena.map.rpt:; fe_error ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
flyrena.map.rpt:; mrb_l ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; usecond ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; utick ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; nv ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
flyrena.map.rpt:; d ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; q ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; afull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; rx_ferr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; fifo_full ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
flyrena.map.rpt:; Rx ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
flyrena.map.rpt:; Tx_busy ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; Tx_full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; Tx_empty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; Rx_busy ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; Rx_brk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; Rx_attn ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; rbi ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
flyrena.map.rpt:; halffull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; c0 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; c2 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; c3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; c4 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at flyrena.v(203)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/serializer.v(188)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/pha.v(62)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(424)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(426)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(428)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(433)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(435)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(437)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(451)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(478)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(840)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(842)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(844)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(846)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(942)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(956)
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(128): Parameter Declaration in module "pps_gen" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(129): Parameter Declaration in module "pps_gen" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(96): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(97): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(98): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(99): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(100): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(118): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(166): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(168): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(169): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(170): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(171): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(186): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(485): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(503): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(521): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(551): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(609): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(610): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(626): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(627): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(628): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(629): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(631): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(632): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(633): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(446): Parameter Declaration in module "memasync32ee" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(447): Parameter Declaration in module "memasync32ee" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(448): Parameter Declaration in module "memasync32ee" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(656): Parameter Declaration in module "memasync16ee48" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(657): Parameter Declaration in module "memasync16ee48" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(658): Parameter Declaration in module "memasync16ee48" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(97): truncated value with size 32 to match size of target (4)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(253): truncated value with size 32 to match size of target (8)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(255): truncated value with size 32 to match size of target (8)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(70): truncated value with size 32 to match size of target (3)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(141): truncated value with size 32 to match size of target (10)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(162): truncated value with size 32 to match size of target (10)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(12): truncated value with size 32 to match size of target (10)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at secondcyclone.v(49): truncated value with size 32 to match size of target (8)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at secondcyclone.v(60): truncated value with size 32 to match size of target (5)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_master_adc.v(99): truncated value with size 32 to match size of target (4)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at adc_data.v(25): truncated value with size 32 to match size of target (2)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(1269): truncated value with size 32 to match size of target (16)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(1292): truncated value with size 32 to match size of target (2)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at icucore.v(138): truncated value with size 32 to match size of target (10)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at icucore.v(149): truncated value with size 32 to match size of target (16)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(90): truncated value with size 32 to match size of target (4)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(347): truncated value with size 32 to match size of target (9)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(360): truncated value with size 32 to match size of target (4)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at heteptcore.v(220): truncated value with size 32 to match size of target (14)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at secondcyclone.v(133): truncated value with size 32 to match size of target (5)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(73): truncated value with size 32 to match size of target (18)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(75): truncated value with size 32 to match size of target (18)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(142): truncated value with size 32 to match size of target (4)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(220): truncated value with size 32 to match size of target (4)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(237): truncated value with size 32 to match size of target (16)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(251): truncated value with size 32 to match size of target (13)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at crc.v(65): truncated value with size 32 to match size of target (4)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at crc.v(18): truncated value with size 32 to match size of target (16)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at crc.v(22): truncated value with size 32 to match size of target (16)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at crc.v(27): truncated value with size 32 to match size of target (16)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(237): truncated value with size 32 to match size of target (16)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(259): truncated value with size 32 to match size of target (27)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(261): truncated value with size 32 to match size of target (27)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(263): truncated value with size 32 to match size of target (27)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(388): truncated value with size 32 to match size of target (13)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(390): truncated value with size 32 to match size of target (13)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(395): truncated value with size 32 to match size of target (4)
flyrena.map.rpt:Warning (10030): Net "clkdiv[2..0]" at uart.v(380) has no driver or initial value, using a default initial value '0'
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at fifo.v(47): truncated value with size 32 to match size of target (8)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at fifo.v(61): truncated value with size 32 to match size of target (6)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at fifo.v(63): truncated value with size 32 to match size of target (6)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at fifo.v(98): truncated value with size 32 to match size of target (8)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at fifo.v(106): truncated value with size 32 to match size of target (6)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at heteptcore.v(550): truncated value with size 32 to match size of target (9)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at heteptcore.v(551): truncated value with size 32 to match size of target (9)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at heteptcore.v(552): truncated value with size 32 to match size of target (9)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at heteptcore.v(553): truncated value with size 32 to match size of target (9)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at heteptcore.v(554): truncated value with size 32 to match size of target (9)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at heteptcore.v(555): truncated value with size 32 to match size of target (9)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at heteptcore.v(556): truncated value with size 32 to match size of target (9)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at heteptcore.v(557): truncated value with size 32 to match size of target (9)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at heteptcore.v(558): truncated value with size 32 to match size of target (9)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at heteptcore.v(559): truncated value with size 32 to match size of target (9)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at heteptcore.v(621): truncated value with size 32 to match size of target (3)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at heteptcore.v(639): truncated value with size 32 to match size of target (8)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(477): truncated value with size 32 to match size of target (16)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at counters.v(16): truncated value with size 32 to match size of target (16)
flyrena.map.rpt:Warning (10036): Verilog HDL or VHDL warning at backend.v(211): object "t_count" assigned a value but never read
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at msg_regs.v(88): truncated value with size 32 to match size of target (16)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at msg_regs.v(95): truncated value with size 32 to match size of target (16)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at msg_regs.v(106): truncated value with size 32 to match size of target (16)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at msg_regs.v(117): truncated value with size 32 to match size of target (4)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at msg_regs.v(119): truncated value with size 32 to match size of target (4)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at l3code.v(218): truncated value with size 32 to match size of target (24)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at l3code.v(219): truncated value with size 32 to match size of target (11)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at counters.v(82): truncated value with size 32 to match size of target (7)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at counters.v(116): truncated value with size 32 to match size of target (30)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(21): truncated value with size 32 to match size of target (6)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(24): truncated value with size 32 to match size of target (6)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(27): truncated value with size 32 to match size of target (4)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(28): truncated value with size 32 to match size of target (27)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(39): truncated value with size 27 to match size of target (12)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(21): truncated value with size 32 to match size of target (7)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(24): truncated value with size 32 to match size of target (7)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(39): truncated value with size 27 to match size of target (3)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at ppsschedule.v(108): truncated value with size 32 to match size of target (12)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at ppsschedule.v(121): truncated value with size 32 to match size of target (3)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at ppsschedule.v(124): truncated value with size 32 to match size of target (3)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at ppsschedule.v(171): truncated value with size 32 to match size of target (6)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at ppsschedule.v(183): truncated value with size 32 to match size of target (24)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at ppsschedule.v(220): truncated value with size 32 to match size of target (8)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(27): truncated value with size 32 to match size of target (4)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(47): truncated value with size 32 to match size of target (4)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(27): truncated value with size 32 to match size of target (3)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(47): truncated value with size 32 to match size of target (3)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(322): truncated value with size 32 to match size of target (19)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(323): truncated value with size 32 to match size of target (8)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(329): truncated value with size 32 to match size of target (8)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(341): truncated value with size 32 to match size of target (26)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at eeprom.v(131): truncated value with size 32 to match size of target (2)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at eeprom.v(136): truncated value with size 32 to match size of target (7)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at eeprom.v(137): truncated value with size 32 to match size of target (8)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at eeprom.v(157): truncated value with size 32 to match size of target (14)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(72): truncated value with size 32 to match size of target (2)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(78): truncated value with size 32 to match size of target (5)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(96): truncated value with size 32 to match size of target (2)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(101): truncated value with size 32 to match size of target (5)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(207): truncated value with size 32 to match size of target (24)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(222): truncated value with size 32 to match size of target (5)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(248): truncated value with size 32 to match size of target (4)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(256): truncated value with size 32 to match size of target (9)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(260): truncated value with size 32 to match size of target (9)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(46): truncated value with size 32 to match size of target (8)
flyrena.map.rpt:Warning (10036): Verilog HDL or VHDL warning at processor.v(286): object "mux_jump" assigned a value but never read
flyrena.map.rpt:Warning (10036): Verilog HDL or VHDL warning at processor.v(331): object "go_addi" assigned a value but never read
flyrena.map.rpt:Warning (10036): Verilog HDL or VHDL warning at processor.v(331): object "go_add" assigned a value but never read
flyrena.map.rpt:Warning (10036): Verilog HDL or VHDL warning at processor.v(331): object "go_sub" assigned a value but never read
flyrena.map.rpt:Warning (10036): Verilog HDL or VHDL warning at processor.v(331): object "go_log" assigned a value but never read
flyrena.map.rpt:Warning (10036): Verilog HDL or VHDL warning at processor.v(331): object "go_cmp" assigned a value but never read
flyrena.map.rpt:Warning (10036): Verilog HDL or VHDL warning at processor.v(331): object "go_trim" assigned a value but never read
flyrena.map.rpt:Warning (10036): Verilog HDL or VHDL warning at processor.v(331): object "go_brng" assigned a value but never read
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(449): truncated value with size 32 to match size of target (29)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(450): truncated value with size 32 to match size of target (29)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(459): truncated value with size 32 to match size of target (29)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(466): truncated value with size 32 to match size of target (29)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(474): truncated value with size 32 to match size of target (29)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(479): truncated value with size 32 to match size of target (29)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(487): truncated value with size 32 to match size of target (29)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(494): truncated value with size 32 to match size of target (29)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(503): truncated value with size 29 to match size of target (1)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at adder.v(46): truncated value with size 32 to match size of target (28)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at adder.v(55): truncated value with size 32 to match size of target (28)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at adderi.v(23): truncated value with size 32 to match size of target (28)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at mult.v(27): truncated value with size 45 to match size of target (29)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at log7to4.v(33): truncated value with size 32 to match size of target (5)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at log7to4.v(36): truncated value with size 37 to match size of target (7)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at bitrange.v(15): truncated value with size 32 to match size of target (29)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at bitrange.v(16): truncated value with size 32 to match size of target (29)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at ppsschedule.v(325): truncated value with size 32 to match size of target (11)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at ppsschedule.v(326): truncated value with size 32 to match size of target (12)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at ppsschedule.v(439): truncated value with size 32 to match size of target (3)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at compression.v(171): truncated value with size 32 to match size of target (7)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at compression.v(186): truncated value with size 32 to match size of target (26)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at compression.v(196): truncated value with size 32 to match size of target (2)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at encode.v(35): truncated value with size 32 to match size of target (5)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at encode.v(84): truncated value with size 32 to match size of target (5)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at encode.v(86): truncated value with size 32 to match size of target (5)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at encode.v(91): truncated value with size 32 to match size of target (4)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at encode.v(93): truncated value with size 32 to match size of target (4)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at encode.v(116): truncated value with size 32 to match size of target (26)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at encode.v(117): truncated value with size 32 to match size of target (26)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(21): truncated value with size 32 to match size of target (6)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(24): truncated value with size 32 to match size of target (6)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(39): truncated value with size 24 to match size of target (12)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at log2by8.v(24): truncated value with size 32 to match size of target (5)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at log2by8.v(27): truncated value with size 32 to match size of target (5)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(386): truncated value with size 32 to match size of target (6)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(388): truncated value with size 32 to match size of target (6)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(400): truncated value with size 32 to match size of target (12)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(435): truncated value with size 32 to match size of target (12)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at opheater.v(36): truncated value with size 4 to match size of target (3)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at opheater.v(39): truncated value with size 16 to match size of target (13)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at opheater.v(51): truncated value with size 32 to match size of target (8)
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at opheater.v(64): truncated value with size 32 to match size of target (24)
flyrena.map.rpt:Warning: Synthesized away the following node(s):
flyrena.map.rpt: Warning: Synthesized away the following RAM node(s):
flyrena.map.rpt: Warning (14320): Synthesized away node "heteptdig_core:dig|backend:back|eventbuffer:pha|mem29x128edac:pha_accounting_mem|mem36:m|memDxA:m|altsyncram:altsyncram_component|altsyncram_edp1:auto_generated|q_b[0]"
flyrena.map.rpt: Warning (14320): Synthesized away node "heteptdig_core:dig|backend:back|eventbuffer:pha|mem64x128edac:mem|mem72:m|memDxA:m|altsyncram:altsyncram_component|altsyncram_fdp1:auto_generated|q_b[0]"
flyrena.map.rpt: Warning (14320): Synthesized away node "heteptdig_core:dig|backend:back|eeprom_page:mp2ee|mem36:mem|memDxA:m|altsyncram:altsyncram_component|altsyncram_edp1:auto_generated|q_b[32]"
flyrena.map.rpt: Warning (14320): Synthesized away node "heteptdig_core:dig|backend:back|eeprom_page:mp2ee|mem36:mem|memDxA:m|altsyncram:altsyncram_component|altsyncram_edp1:auto_generated|q_b[33]"
flyrena.map.rpt: Warning (14320): Synthesized away node "heteptdig_core:dig|backend:back|eeprom_page:mp2ee|mem36:mem|memDxA:m|altsyncram:altsyncram_component|altsyncram_edp1:auto_generated|q_b[34]"
flyrena.map.rpt: Warning (14320): Synthesized away node "heteptdig_core:dig|backend:back|eeprom_page:mp2ee|mem36:mem|memDxA:m|altsyncram:altsyncram_component|altsyncram_edp1:auto_generated|q_b[35]"
flyrena.map.rpt:Warning: 23 hierarchies have connectivity warnings - see the Connectivity Checks report folder
flyrena.map.rpt:Warning: The following bidir pins have no drivers
flyrena.map.rpt: Warning: Bidir "adc_mode" has no driver
flyrena.map.rpt:Warning: Output pins are stuck at VCC or GND
flyrena.map.rpt: Warning (13410): Pin "debug[6]" is stuck at GND
flyrena.map.rpt: Warning (13410): Pin "debug[5]" is stuck at GND
flyrena.map.rpt: Warning (13410): Pin "debug[1]" is stuck at GND
flyrena.map.rpt:Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" has parameters clk0_multiply_by and clk0_divide_by specified but port CLK[0] is not connected
flyrena.map.rpt:Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" has parameters clk0_multiply_by and clk0_divide_by specified but port CLK[0] is not connected
flyrena.map.rpt:Warning: Design contains 16 input pin(s) that do not drive logic
flyrena.map.rpt: Warning (15610): No output dependent on input pin "clk_T1"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_dco"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[0]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[1]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[2]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[3]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[4]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[5]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[6]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[7]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[8]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[9]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[10]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[11]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[12]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[13]"
flyrena.map.rpt:Info: Quartus II Analysis & Synthesis was successful. 0 errors, 239 warnings
flyrena.sta.rpt:Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings
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