flyrena.asm.rpt:Info: Quartus II Assembler was successful. 0 errors, 0 warnings
flyrena.fit.rpt: 5. I/O Assignment Warnings
flyrena.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
flyrena.fit.rpt:; I/O Assignment Warnings ;
flyrena.fit.rpt:Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.
flyrena.fit.rpt:Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
flyrena.fit.rpt:Warning: Following 10 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
flyrena.fit.rpt: Warning: Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)"
flyrena.fit.rpt: Warning: Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)"
flyrena.fit.rpt: Warning: Pin "adc_clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "adc_clk(n)"
flyrena.fit.rpt: Warning: Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
flyrena.fit.rpt: Warning: Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
flyrena.fit.rpt: Warning: Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
flyrena.fit.rpt: Warning: Pin "ARxC" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARxC(n)"
flyrena.fit.rpt: Warning: Pin "CRx" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "CRx(n)"
flyrena.fit.rpt: Warning: Pin "ARxD" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "ARxD(n)"
flyrena.fit.rpt: Warning: Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)"
flyrena.fit.rpt:Warning: Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
flyrena.fit.rpt:Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" output port clk[1] feeds output pin "ATxCP~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
flyrena.fit.rpt:Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" output port clk[1] feeds output pin "ATxCN~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
flyrena.fit.rpt:Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
flyrena.fit.rpt:Warning: Following 1 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
flyrena.map.rpt:; afull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; empty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; empty3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; empty3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; empty3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; empty3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; empty3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; empty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; empty3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; error ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; single ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; error ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; single ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; pend ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; busy ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; w ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
flyrena.map.rpt:; mrb_w ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
flyrena.map.rpt:; fe_single ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
flyrena.map.rpt:; fe_error ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
flyrena.map.rpt:; mrb_l ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; usecond ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; utick ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; nv ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
flyrena.map.rpt:; afull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; rx_ferr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; fifo_full ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
flyrena.map.rpt:; Rx ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
flyrena.map.rpt:; Tx_busy ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; Tx_full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; Tx_empty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; Rx_busy ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; Rx_brk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; Rx_attn ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; rbi ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
flyrena.map.rpt:; halffull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; c0 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; c2 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; c3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:; c4 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at flyrena.v(203)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/serializer.v(188)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/pha.v(62)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(424)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(426)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(428)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(433)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(435)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(437)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(451)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(478)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(840)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(842)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(844)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(846)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(942)
flyrena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../sirena/altera/memport.v(956)
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(128): Parameter Declaration in module "pps_gen" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(129): Parameter Declaration in module "pps_gen" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(96): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(97): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(98): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(99): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(100): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(118): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(166): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(168): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(169): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(170): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(171): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(186): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(485): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(503): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(521): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(551): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(609): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(610): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(626): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(627): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(628): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(629): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(631): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(632): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(633): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(446): Parameter Declaration in module "memasync32ee" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(447): Parameter Declaration in module "memasync32ee" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(448): Parameter Declaration in module "memasync32ee" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(656): Parameter Declaration in module "memasync16ee48" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(657): Parameter Declaration in module "memasync16ee48" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(658): Parameter Declaration in module "memasync16ee48" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
flyrena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(97): truncated value with size 32 to match size of target (4)
flyrena.map.rpt: Warning (13410): Pin "debug[1]" is stuck at GND
flyrena.map.rpt:Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" has parameters clk0_multiply_by and clk0_divide_by specified but port CLK[0] is not connected
flyrena.map.rpt:Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" has parameters clk0_multiply_by and clk0_divide_by specified but port CLK[0] is not connected
flyrena.map.rpt:Warning: Design contains 16 input pin(s) that do not drive logic
flyrena.map.rpt: Warning (15610): No output dependent on input pin "clk_T1"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_dco"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[0]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[1]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[2]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[3]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[4]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[5]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[6]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[7]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[8]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[9]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[10]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[11]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[12]"
flyrena.map.rpt: Warning (15610): No output dependent on input pin "adc_d[13]"
