solo_altera/sirena/altera/sirenacntr.warnings

sirenacntr.asm.rpt:Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
sirenacntr.fit.rpt:  5. I/O Assignment Warnings
sirenacntr.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
sirenacntr.fit.rpt:; I/O Assignment Warnings                            ;
sirenacntr.fit.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
sirenacntr.fit.rpt:Warning (15901): PLL "pll384:pll0|altpll:altpll_component|altpll_r273:auto_generated|pll1" has parameter clk0_counter set to C0 specified but port CLK[0] is not connected
sirenacntr.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
sirenacntr.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
sirenacntr.fit.rpt:Warning (176674): Following 7 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
sirenacntr.fit.rpt:    Warning (176118): Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)"
sirenacntr.fit.rpt:    Warning (176118): Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)"
sirenacntr.fit.rpt:    Warning (176118): Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)"
sirenacntr.fit.rpt:    Warning (176118): Pin "FE_clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "FE_clk(n)"
sirenacntr.fit.rpt:    Warning (176118): Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
sirenacntr.fit.rpt:    Warning (176118): Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
sirenacntr.fit.rpt:    Warning (176118): Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
sirenacntr.fit.rpt:Warning (176251): Ignoring some wildcard destinations of fast I/O register assignments
sirenacntr.fit.rpt:Warning (169064): Following 16 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
sirenacntr.fit.rpt:Info: Quartus II 32-bit Fitter was successful. 0 errors, 14 warnings
sirenacntr.map.rpt:; halffull ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
sirenacntr.map.rpt:; fifo_empty      ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
sirenacntr.map.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(427)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(429)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(431)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(436)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(438)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(440)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(454)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(481)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(843)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(845)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(847)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(849)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(945)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(959)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(1085)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(1087)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(1089)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(1091)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(1193)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(1205)
sirenacntr.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(1217)
sirenacntr.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(449): Parameter Declaration in module "memasync32ee" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
sirenacntr.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(450): Parameter Declaration in module "memasync32ee" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
sirenacntr.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(451): Parameter Declaration in module "memasync32ee" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
sirenacntr.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(659): Parameter Declaration in module "memasync16ee48" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
sirenacntr.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(660): Parameter Declaration in module "memasync16ee48" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
sirenacntr.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(661): Parameter Declaration in module "memasync16ee48" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
sirenacntr.map.rpt:Warning (10230): Verilog HDL assignment warning at sirenacntr.v(162): truncated value with size 32 to match size of target (19)
sirenacntr.map.rpt:Warning (10230): Verilog HDL assignment warning at sirenacntr.v(233): truncated value with size 32 to match size of target (16)
sirenacntr.map.rpt:Warning (10034): Output port "Tx" at sirenacntr.v(19) has no driver
sirenacntr.map.rpt:Warning (10034): Output port "debug" at sirenacntr.v(26) has no driver
sirenacntr.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(97): truncated value with size 32 to match size of target (4)
sirenacntr.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
sirenacntr.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(254): truncated value with size 32 to match size of target (8)
sirenacntr.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(256): truncated value with size 32 to match size of target (8)
sirenacntr.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(70): truncated value with size 32 to match size of target (3)
sirenacntr.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(150): truncated value with size 32 to match size of target (10)
sirenacntr.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(171): truncated value with size 32 to match size of target (10)
sirenacntr.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (5)
sirenacntr.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (10)
sirenacntr.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(1328): truncated value with size 32 to match size of target (2)
sirenacntr.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(27): truncated value with size 32 to match size of target (3)
sirenacntr.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(47): truncated value with size 32 to match size of target (3)
sirenacntr.map.rpt:Warning (10230): Verilog HDL assignment warning at nmcounter.v(187): truncated value with size 32 to match size of target (2)
sirenacntr.map.rpt:Warning (10230): Verilog HDL assignment warning at nmcounter.v(193): truncated value with size 32 to match size of target (7)
sirenacntr.map.rpt:Warning (10230): Verilog HDL assignment warning at nmcounter.v(195): truncated value with size 32 to match size of target (7)
sirenacntr.map.rpt:Warning (10230): Verilog HDL assignment warning at nmcounter.v(271): truncated value with size 32 to match size of target (16)
sirenacntr.map.rpt:Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder
sirenacntr.map.rpt:Warning (13039): The following bidir pins have no drivers
sirenacntr.map.rpt:    Warning (13040): Bidir "FE_port[0]" has no driver
sirenacntr.map.rpt:    Warning (13040): Bidir "FE_port[1]" has no driver
sirenacntr.map.rpt:    Warning (13040): Bidir "FE_port[2]" has no driver
sirenacntr.map.rpt:    Warning (13040): Bidir "FE_port[3]" has no driver
sirenacntr.map.rpt:    Warning (13040): Bidir "FE_port[4]" has no driver
sirenacntr.map.rpt:    Warning (13040): Bidir "FE_port[5]" has no driver
sirenacntr.map.rpt:    Warning (13040): Bidir "FE_port[6]" has no driver
sirenacntr.map.rpt:    Warning (13040): Bidir "FE_port[7]" has no driver
sirenacntr.map.rpt:    Warning (13040): Bidir "FE_port[8]" has no driver
sirenacntr.map.rpt:    Warning (13040): Bidir "FE_port[9]" has no driver
sirenacntr.map.rpt:    Warning (13040): Bidir "FE_port[10]" has no driver
sirenacntr.map.rpt:    Warning (13040): Bidir "FE_port[11]" has no driver
sirenacntr.map.rpt:    Warning (13040): Bidir "FE_port[12]" has no driver
sirenacntr.map.rpt:    Warning (13040): Bidir "FE_port[13]" has no driver
sirenacntr.map.rpt:    Warning (13040): Bidir "FE_port[14]" has no driver
sirenacntr.map.rpt:    Warning (13040): Bidir "FE_port[15]" has no driver
sirenacntr.map.rpt:Warning (13024): Output pins are stuck at VCC or GND
sirenacntr.map.rpt:    Warning (13410): Pin "sram_ce[2]" is stuck at VCC
sirenacntr.map.rpt:    Warning (13410): Pin "Tx[2]" is stuck at GND
sirenacntr.map.rpt:    Warning (13410): Pin "Tx[1]" is stuck at GND
sirenacntr.map.rpt:    Warning (13410): Pin "debug[6]" is stuck at GND
sirenacntr.map.rpt:    Warning (13410): Pin "debug[5]" is stuck at GND
sirenacntr.map.rpt:    Warning (13410): Pin "debug[4]" is stuck at GND
sirenacntr.map.rpt:Warning (15901): PLL "pll384:pll0|altpll:altpll_component|altpll_r273:auto_generated|pll1" has parameter clk0_counter set to C0 specified but port CLK[0] is not connected
sirenacntr.map.rpt:Warning (21074): Design contains 7 input pin(s) that do not drive logic
sirenacntr.map.rpt:    Warning (15610): No output dependent on input pin "clk_T1"
sirenacntr.map.rpt:    Warning (15610): No output dependent on input pin "trigger"
sirenacntr.map.rpt:    Warning (15610): No output dependent on input pin "Rx[4]"
sirenacntr.map.rpt:    Warning (15610): No output dependent on input pin "Rx[3]"
sirenacntr.map.rpt:    Warning (15610): No output dependent on input pin "Rx[2]"
sirenacntr.map.rpt:    Warning (15610): No output dependent on input pin "Rx[1]"
sirenacntr.map.rpt:    Warning (15610): No output dependent on input pin "FE_clk"
sirenacntr.map.rpt:Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 82 warnings
sirenacntr.sta.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
sirenacntr.sta.rpt:Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning