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doc
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l3trigger.tex: added information about compare_l3_pha.py
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2014-11-18 16:54:42 +00:00 |
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dps
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First try at pipe.py and dps-simulator
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2014-11-17 14:46:47 +00:00 |
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encode
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compression sim: strange STEP FS case
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2018-01-23 07:01:03 +00:00 |
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hk
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add hkspi to sirena
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2012-07-16 19:48:42 +00:00 |
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l3
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l3.tex: Fix TRIM description.
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2019-02-20 11:23:14 +00:00 |
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backend.gold
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backend: implement msg('h12) write SRAM
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2019-11-20 21:28:58 +00:00 |
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backend.gtkw
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backend testjig: POKE large numbers into hist memory
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2015-01-14 00:20:00 +00:00 |
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backend.v
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backend: fix quartus warnings about port size mismatch
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2020-11-30 19:44:12 +00:00 |
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baud.py
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uart: change nominal bit rate to 114942 baud
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2013-12-03 21:24:39 +00:00 |
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baudgen_test.v
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baudgen: fix
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2018-04-26 22:01:58 +00:00 |
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compression.txt
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compresion: fixing the rounding, ...
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2011-11-09 16:17:27 +00:00 |
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core.v
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lost+found
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2012-07-13 14:27:42 +00:00 |
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counters.gtkw
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counters: fix EDAC reporting
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2018-01-26 13:48:16 +00:00 |
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counters.v
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solo counters: fix float 8/16 overflow, signedness
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2022-05-05 13:26:39 +00:00 |
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crc.v
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crc: implement CRC Verification of Compliance from the TM-TC-ICD
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2013-10-30 22:53:24 +00:00 |
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crc_v3.txt
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crc doc
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2018-07-11 12:22:10 +00:00 |
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dps_conf_clear.py
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dps_table.py: shifted dps configuration in external files; added documentation folder /sirena/altera/doc/ for latex documentation
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2014-11-10 13:34:42 +00:00 |
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dps_conf_simple_hist.py
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l3trigger.tex: edited section about DPS, dps_table.py: binary flag for files included, standard output now stdout instead of stderr
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2014-11-10 15:26:41 +00:00 |
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dps_step.py
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dps_table.py:
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2015-01-26 16:28:07 +00:00 |
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dps_test.py
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Added dps_test.py, several changes in dps_table for additional functionality
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2015-01-09 09:21:52 +00:00 |
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eeprom.v
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eeprom page write:
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2018-03-04 20:51:59 +00:00 |
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encschedule.gold
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encschedule: gold for old low rate algorithm
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2015-04-26 19:37:15 +00:00 |
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ept_data_desc.txt
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ept_data_desc.txt: minor corrections
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2014-11-06 14:56:19 +00:00 |
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ept_dps.iv
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l3win_test: new simulatioon, to be debugged
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2016-02-29 19:50:57 +00:00 |
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evgen.gtkw
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sirena: evgen_hetept complete and functional
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2013-10-13 22:54:43 +00:00 |
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evgen.v
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evgen: l2 trigger updated
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2015-05-28 21:47:48 +00:00 |
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fifo.gtkw
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replace spififo with EDAC bfifo(16-bit) in secondcyclone slave
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2013-05-21 21:23:36 +00:00 |
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fifo.v
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bfifo: fix full flag at address wrap
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2014-05-05 21:47:02 +00:00 |
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floats.v
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verilog: fix a few nonblocking assignment s
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2015-03-17 23:58:36 +00:00 |
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hamming.v
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hamming: s64_edac for MEPS sampleram
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2019-10-15 15:00:00 +00:00 |
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het-ept-step-telemetry.tex
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finished?\, to be reviewed
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2013-07-02 15:09:38 +00:00 |
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hetept_himac_l1l2.py
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ppss_table: for HIMAC streaming mode
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2015-01-14 09:42:45 +00:00 |
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hetept_himac_low_thresholds_fullept_l1l2.py
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hetept_himac: l1l2 version with full readout for EPT triggers
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2015-01-19 07:56:00 +00:00 |
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hetept_himac_low_thresholds_l1l2.py
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hetept himac: l1l2 low thresolds, 100keV in EPT
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2015-01-15 10:45:33 +00:00 |
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hetept_nominal.py
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Beginning of a dataproduct compiler
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2013-05-27 20:32:55 +00:00 |
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hetept_test_l1l2.py
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l1l2 trigger: update for HIMAC tests
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2015-01-14 12:58:09 +00:00 |
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historam.v
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work on memory interfaces
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2012-02-25 19:51:01 +00:00 |
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icu-message.txt
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backend: implement msg('h12) write SRAM
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2019-11-20 21:28:58 +00:00 |
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icucore.qpf
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icucore altera built, but with bogus connections, not reviewed
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2013-06-10 15:35:20 +00:00 |
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icucore.qsf
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SpWire in sirena
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2018-11-02 16:38:42 +00:00 |
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icucore.sdc
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serializer demux: do not use 5-bit counter @ 384 MHz
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2013-12-20 07:03:24 +00:00 |
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icucore.v
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icucore: compile option UART_PARITY
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2017-03-21 19:41:06 +00:00 |
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icucore.warnings
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serializer demux: do not use 5-bit counter @ 384 MHz
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2013-12-20 07:03:24 +00:00 |
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itof.gold
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itof: Fix BUG in itouf
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2015-01-13 23:14:02 +00:00 |
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l3code.gtkw
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use bfifo as txfifo
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2012-12-18 12:22:13 +00:00 |
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l3code.v
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merge C'E4 dig fixes into trunc
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2017-03-13 11:01:27 +00:00 |
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l3registerfile.gold
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fix we
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2013-06-30 01:02:57 +00:00 |
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l3registerfile.gtkw
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implement constant read latency, ra/re registered at input
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2012-07-23 14:19:34 +00:00 |
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l3registerfile.v
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l3registerfile: add .clear command
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2015-05-12 20:44:57 +00:00 |
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l3test-step.ev
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step.l3: L3 trigger code for STEP
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2015-04-19 03:34:56 +00:00 |
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l3test-step.l3v
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step.l3: L3 trigger code for STEP
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2015-04-19 03:34:56 +00:00 |
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l3test.dat
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i128event.py: Added generic PHA event to process arbitrary data.
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2015-01-07 16:35:37 +00:00 |
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l3test.gold
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l3test: simulate one STEP event
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2015-04-18 20:46:38 +00:00 |
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l3test.gtkw
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l3test: gtkw
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2015-04-23 13:32:31 +00:00 |
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l3test.v
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l3test: add EPT events
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2015-04-26 21:29:04 +00:00 |
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l3test_ept.ev
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l3test: add EPT events
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2015-04-26 21:29:04 +00:00 |
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l3trig.v
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first code
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2011-01-04 11:41:47 +00:00 |
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l3win_test.v
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l3win_test: 50ms @ 24MHz
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2016-03-04 18:04:27 +00:00 |
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log2by8.v
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log2by8: add comments for decoding hints
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2015-05-11 13:49:53 +00:00 |
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Makefile
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memport mem_sqi
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2024-03-03 01:04:52 +00:00 |
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mem8port.v
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lost+found
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2011-05-17 18:27:09 +00:00 |
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mem_sqi.gold
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mem_sqi: remove conf_w interface, use MSB of address as command flag
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2024-03-03 21:50:48 +00:00 |
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mem_sqi.gtkwave
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mem_sqi: remove conf_w interface, use MSB of address as command flag
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2024-03-03 21:50:48 +00:00 |
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memory.v
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hvps setup for Semra
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2012-07-24 09:23:03 +00:00 |
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memport.gold
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eeprom_page: fix write cycle time bug
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2015-02-17 22:45:58 +00:00 |
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memport.gtkw
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memport: memasync8m for C'E4
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2016-11-21 20:40:33 +00:00 |
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memport.v
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memport/memread: fix clear
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2024-05-22 08:44:05 +00:00 |
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message.v
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sirenaspw: fix MCLK, provide status
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2018-12-03 22:31:08 +00:00 |
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msg_regs.v
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msg_regs: improve sim startup, issue wait at ack through R=1 ports
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2015-03-05 15:11:51 +00:00 |
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mult.gtkw
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new multiplier implementation
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2013-02-22 21:24:52 +00:00 |
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pha.v
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backend...:
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2015-03-18 19:41:12 +00:00 |
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pps_gen.gtkw
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pps_gen fixed
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2013-06-10 14:22:40 +00:00 |
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ppsschedule.gtkw
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move file from flyrena to sirena
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2013-01-06 16:08:59 +00:00 |
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ppsschedule.hex
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move file from flyrena to sirena
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2013-01-06 16:08:59 +00:00 |
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ppsschedule.v
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ppsschedule: comment typo
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2015-05-24 13:06:56 +00:00 |
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processor.gold
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renumber the condition bits
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2013-05-27 20:10:21 +00:00 |
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processor.gtkw
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L3 processor reimplemented
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2013-03-08 16:04:10 +00:00 |
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s18_test.gtkw
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hamming: 18 bit brutto, 12 bit netto
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2019-02-10 23:21:20 +00:00 |
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sirena.gold
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eeprom exec: fix data port, sirena sim
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2016-10-02 09:30:29 +00:00 |
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sirena.gtkw
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eeprom exec: fix data port, sirena sim
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2016-10-02 09:30:29 +00:00 |
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sirena.qpf
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adaption from irena
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2010-10-06 23:07:43 +00:00 |
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sirena.qsf
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sirena: with spacewire
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2018-11-21 16:35:35 +00:00 |
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sirena.sdc
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sirena: synth fixes
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2014-02-11 22:35:53 +00:00 |
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sirena.v
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sirena: rmsg, frontend resets
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2018-11-28 23:31:00 +00:00 |
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sirena.warnings
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backend: fix quartus warnings about port size mismatch
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2020-11-30 19:44:12 +00:00 |
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sirena_ce4.qpf
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sirena_ce4: altera target
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2016-09-29 14:15:28 +00:00 |
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sirena_ce4.qsf
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SpWire in sirena
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2018-11-02 16:38:42 +00:00 |
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sirena_ce4.sdc
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C'E4 toplevel verilog
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2016-10-13 09:11:30 +00:00 |
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sirena_ce4.warnings
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sirena C'E4: power fault is XOR of frontend and backend config
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2016-12-14 15:13:59 +00:00 |
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sirena_test.v
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C'E4 ana/dig simulation
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2016-10-04 19:19:08 +00:00 |
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sirenacntr.gtkw
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sirenacntr: bitfile with nmcounter module
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2018-02-16 10:24:42 +00:00 |
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sirenacntr.qpf
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sirenacntr: Torsten's internship project, empty sirena template
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2018-02-11 15:37:17 +00:00 |
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sirenacntr.qsf
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sirenacntr: bitfile with nmcounter module
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2018-02-16 10:24:42 +00:00 |
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sirenacntr.sdc
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sirenacntr: bitfile with nmcounter module
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2018-02-16 10:24:42 +00:00 |
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sirenacntr.v
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sirenacntr: bitfile with nmcounter module
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2018-02-16 10:24:42 +00:00 |
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sirenacntr.warnings
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nmcounter: fix counters numbered > 32
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2018-02-16 11:56:55 +00:00 |
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sirenacore.v
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sirenacore: fix fifo_push[1]
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2019-01-15 12:52:08 +00:00 |
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sirenaspw.qpf
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sirena: with spacewire
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2018-11-21 16:35:35 +00:00 |
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sirenaspw.qsf
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sirenaspw: fix MCLK, provide status
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2018-12-03 22:31:08 +00:00 |
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sirenaspw.sdc
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sirena: with spacewire
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2018-11-21 16:35:35 +00:00 |
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sirenaspw.warnings
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sirenacore: fix fifo_push[1] warnings
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2019-01-16 10:24:34 +00:00 |
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SpW_message.gtkw
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message: SpW
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2016-11-23 23:57:02 +00:00 |
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spwsirena.qpf
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sirena: with spacewire
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2018-11-21 16:35:35 +00:00 |
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spwsirena.qsf
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sirena: with spacewire
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2018-11-21 16:35:35 +00:00 |
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spwsirena.sdc
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spwsirena: fix clocks
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2018-11-26 16:36:48 +00:00 |
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spwsirena.warnings
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spwsirena: fix clocks
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2018-11-26 16:36:48 +00:00 |
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step_ppss.py
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step_ppss.py: Added STEP ppss table stub.
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2015-01-27 11:02:19 +00:00 |
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test.l3
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moving towards simulation of EPT events
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2013-05-27 13:29:22 +00:00 |
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uart.gold
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uart: PARITY integration and test work
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2016-09-29 08:24:34 +00:00 |
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uart.gtkw
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uart: PARITY integration and test work
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2016-09-29 08:24:34 +00:00 |
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uart.v
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nmuart: support 7-bit with parity
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2018-12-02 00:29:33 +00:00 |
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uf.gold
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sirena: evgen_hetept complete and functional
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2013-10-13 22:54:43 +00:00 |
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uf.gtkw
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sirena: evgen_hetept complete and functional
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2013-10-13 22:54:43 +00:00 |
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