01e054c3ab
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@8884 bc5caf13-1734-44f8-af43-603852e9ee25
216 lines
7 KiB
Makefile
216 lines
7 KiB
Makefile
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VERILOG=/usr/local/bin/iverilog
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#VERILOG=/usr/bin/iverilog
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VERILOGFLAGS = -v -Wall -Wno-timescale -DSIMULATION $($*_FLAGS) $(IVLFLAGS)
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%.vvp:
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$(VERILOG) $(VERILOGFLAGS) -o $@ $(filter %.v, $^)
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vcd/%.lxt: %.vvp
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$< -lxt2 | tee $*.log
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.PRECIOUS: vcd/%.lxt
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VPATH=.:./l3:./encode:./hk:../../flyrena/altera:../../hetept/altera:../../altera:../../altera/mega:../../altera/actel:../../stein/altera:../../nm64/altera:../../µirena/altera
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SIRENA_DEFS = -DChangE4 -DUART_PARITY=1 -DEVGEN_EPT_HET
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sirena_FLAGS = -s sirena_test -DSIRENACORE -DUART3MHZ -DGENSRAM -DINFERRED_SRAM $(SIRENA_DEFS)
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sirena.vvp: sirena.v sirenacore.v sirena_test.v icucore.v \
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evgen.v floats.v \
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frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
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frontend_test.v fifo8_sim.v serializer.v \
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heteptcore.v backend.v opheater.v \
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message.v uart.v crc.v \
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msg_regs.v ppsschedule.v l3code.v hamming.v \
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ppsschedule.hex memport.v eeprom.v \
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compression.v encode.v itof.v log2by8.v \
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processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v \
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adderi.v mult.v bitrange.v \
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mem.v l3registerfile.v counters.v fifo.v pha.v \
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ept.l3v no_het.l3v por.v
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QUARTUS=/usr/local/quartus/altera13.1/quartus
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export PATH:=$(PATH):$(QUARTUS)/bin
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QDIR=quartus
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$(QDIR)/%.rbf: %.qpf %.qsf %.sdc
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quartus_map $<
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quartus_fit $<
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quartus_asm $<
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quartus_sta $<
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grep -i warning $(QDIR)/$*.*.rpt > $*.warnings
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FRONTEND = conf_reg.v spi_slave.v pll96.v spififo.v frontend.v packetfifo.v
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SIRENA_SOURCES = sirena.v \
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sirenacore.v sirena_test.v \
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evgen.v floats.v \
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frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v \
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frontend_test.v fifo8_sim.v \
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heteptcore.v backend.v opheater.v \
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message.v uart.v crc.v \
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msg_regs.v ppsschedule.v l3code.v hamming.v \
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ppsschedule.hex memport.v eeprom.v \
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compression.v encode.v itof.v \
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processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v \
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adderi.v mult.v bitrange.v \
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mem.v l3registerfile.v counters.v fifo.v pha.v
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SPW_SOURCES = spwirena_core.v SpW.v serializer.v
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$(QDIR)/sirena.rbf: $(SIRENA_SOURCES)
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$(QDIR)/sirena_ce4.rbf: $(SIRENA_SOURCES)
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$(QDIR)/icucore.rbf: sirena.v $(FRONTEND)
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$(QDIR)/spwsirena.rbf: $(SIRENA_SOURCES) $(SPW_SOURCES)
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$(QDIR)/sirenaspw.rbf: $(SIRENA_SOURCES) $(SPW_SOURCES)
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uart.vvp: uart.v fifo8_sim.v
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uart_FLAGS = -DUART_TEST -DALTERA_FIFO8 $(UART_DEFS) -s uart_test
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MESSAGE_FIFO = fifo.v hamming.v mem.v
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# MESSAGE_FIFO = fifo8_sim.v
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message.vvp: message.v crc.v uart.v $(MESSAGE_FIFO)
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message_FLAGS = -DMESSAGE_TEST -DINFERRED_SRAM -s message_test
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SpW_message.vvp: message.v crc.v uart.v SpW.v serializer.v
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SpW_message_FLAGS = -DMESSAGE_TEST -DCCSDS_APID="11'h666" -s SpW_message_test
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memory_FLAGS = -DMEMORY_TEST -s memory_test
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l3registerfile.vvp: l3registerfile.v hamming.v mem.v
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l3registerfile_FLAGS = -DL3REG_TEST -s l3registerfile_test -DINFERRED_SRAM
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l3code.vvp: l3code.v hamming.v message.v uart.v crc.v fifo.v
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l3code_FLAGS = -DL3CODE_TEST -s l3code_test -DINFERRED_SRAM
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hkspi_FLAGS = -DHKSPI_TEST -s hkspi_test
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fifo.vvp: fifo.v hamming.v mem.v
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fifo_FLAGS = -DFIFO_TEST -s fifo_test -DINFERRED_SRAM
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MEM=CE4
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memport_FLAGS = -DMEMPORT_TEST -DM24MHZ -DMEM_$(MEM) -DINFERRED_SRAM -s memport_test
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memport.vvp: memport.v hamming.v eeprom.v mem.v
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backend_FLAGS = -DBACKEND_TEST -s backend_test
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l3win_FLAGS = -s l3win_test -DM24MHZ
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ifeq ($(RAM_ACTEL),No)
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RAMS=mem.v
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backend_FLAGS += -DINFERRED_SRAM
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l3win_FLAGS += -DINFERRED_SRAM
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else
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RAMS=mem.v \
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RAM64K36_sim.v memWxActel.v mem36x128.v mem36x512.v mem72x128.v mem72x256.v \
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mem36x2048.v mem72x1024.v mem72x2048.v mem72x512.v \
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mem36x1024.v mem36x256.v
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backend_FLAGS += -DTARGET_ACTEL
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l3win_FLAGS += -DTARGET_ACTEL
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endif
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backend.vvp: backend.v hamming.v l3code.v l3registerfile.v ppsschedule.v memport.v fifo.v \
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message.v pha.v eeprom.v msg_regs.v counters.v $(RAMS) \
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compression.v encode.v itof.v log2by8.v \
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processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v adderi.v mult.v bitrange.v \
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test.l3v
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l3win.vvp: l3win_test.v backend.v hamming.v l3code.v l3registerfile.v ppsschedule.v memport.v fifo.v \
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message.v pha.v eeprom.v msg_regs.v counters.v $(RAMS) \
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compression.v encode.v itof.v log2by8.v \
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processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v adderi.v mult.v bitrange.v \
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ept.l3v ept_dps.iv
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L3TEST_UNIT = STEP
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l3test_FLAGS = -s l3test -DM24MHZ -DINFERRED_SRAM -D$(L3TEST_UNIT)_PHA
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l3test.vvp: l3test.v backend.v hamming.v l3code.v l3registerfile.v ppsschedule.v memport.v fifo.v \
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message.v pha.v eeprom.v msg_regs.v counters.v $(RAMS) \
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compression.v encode.v itof.v log2by8.v \
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processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v adderi.v mult.v bitrange.v \
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l3test.l3v l3test.ev stein_pha.v countbits.v
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mult.vvp: mult.v
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mult_FLAGS = -DMULT_TEST
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l3regfifo_FLAGS = -DL3REGFIFO_TEST -s fifo_tb
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processor.vvp: processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v adderi.v mult.v bitrange.v
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processor_FLAGS = -DPROCESSOR_TEST -s processor_test
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L3C = l3/l3.py
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L3DIS = l3/l3dis.py
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%.l3c: %.l3 $(L3C) .%.forward
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$(L3C) -g hex -o $@ $<
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%.l3v: %.l3 $(L3C) .%.forward
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$(L3C) -g verilog -vv -o $@ -l $*.l3d $<
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%.l3py: %.l3 $(L3C) .%.forward
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$(L3C) -g python -vv -o $@ -l $*.l3d $<
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.%.forward: %.l3 $(L3C)
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$(L3C) -g hex -o /dev/null $<
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touch $@
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.ept.forward: hetept_config.l3 hetept_pha.l3 ept_calib.l3
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.step.forward: step_config.l3 step_pha.l3 step_calib.l3
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%.l3dis: %.l3c $(L3DIS)
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$(L3DIS) -F 'R%(addr)-3d= %(cond)-3s %(mnem)-5s %(args)-25s # 0x%(instr)08x' $< > $@
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%.l3cc: %.l3dis
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$(L3C) -g hex -o $@ $<
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-diff -u $*.l3c $*.l3cc
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clean:
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rm -f *.l3[cdv] *.l3dis *.l3cc .*.forward *.vvp
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pps_gen_FLAGS = -DPPS_GEN_TEST -s pps_gen_test
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pps_gen.vvp: icucore.v
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$(QDIR)/icucore.rbf: sirena.v icucore.v $(FRONTEND) memory.v uart.v secondcyclone.v
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itof_FLAGS = -DITOF_TEST -s itof_test
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itof.vvp: itof.v
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crc_FLAGS = -DCRC_TEST
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crc.vvp: crc.v
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s72_test.vvp: hamming.v
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s72_test_FLAGS = -DS72_TEST -s s72_test
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s18_test.vvp: hamming.v
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s18_test_FLAGS = -DS18_TEST -s s18_test
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s56_test.vvp: hamming.v
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s56_test_FLAGS = -DS56_TEST -s s56_test
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s64_test.vvp: hamming.v
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s64_test_FLAGS = -DS64_TEST -s s64_test
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evgen.vvp: evgen.v crc.v floats.v
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evgen_FLAGS = -DEVGEN_TEST -s evgen_test
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uf.vvp: floats.v
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uf_FLAGS = -DUF_TEST -s uf_test
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log2by8.vvp: log2by8.v
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log2by8_FLAGS = -DLOG2BY8_TEST -s log2by8_test
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encschedule.vvp: compression.v encode.v ppsschedule.v
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encschedule_FLAGS = -DENCSCHEDULE_TEST -s encschedule_test
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counters.vvp: counters.v mem.v hamming.v pha.v itof.v
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counters_FLAGS = -s counters_test -DCOUNTERS_TEST -DINFERRED_SRAM
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sirenacntr_FLAGS = -s sirenacntr_test -DSIRENACNTR -DSIRENACNTR_TEST \
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-DINFERRED_SRAM
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sirenacntr.vvp: sirenacntr.v memport.v \
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frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
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frontend_test.v fifo8_sim.v serializer.v nmcounter.v mem.v
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$(QDIR)/sirenacntr.rbf: sirenacntr.v memport.v \
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frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
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nmcounter.v mem.v
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baudgen.vvp: baudgen_test.v uart.v
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baudgen_FLAGS = -s baudgen_test
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encode_FLAGS = -DENCODE_TEST -s encode_test
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encode.vvp: encode.v
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mem_sqi_FLAGS = -DMEM_SQI_TEST -s mem_ifc_test
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mem_sqi.vvp: memport.v
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