solo_altera/sirena/altera/Makefile

VERILOG=/usr/local/bin/iverilog
#VERILOG=/usr/bin/iverilog

VERILOGFLAGS = -v -Wall -Wno-timescale -DSIMULATION $($*_FLAGS) $(IVLFLAGS)
%.vvp:
	$(VERILOG) $(VERILOGFLAGS) -o $@ $(filter %.v, $^)

vcd/%.lxt: %.vvp
	$< -lxt2 | tee $*.log

.PRECIOUS: vcd/%.lxt

VPATH=.:./l3:./encode:./hk:../../flyrena/altera:../../hetept/altera:../../altera:../../altera/mega:../../altera/actel:../../stein/altera:../../nm64/altera:../../µirena/altera

SIRENA_DEFS = -DChangE4 -DUART_PARITY=1 -DEVGEN_EPT_HET
sirena_FLAGS = -s sirena_test -DSIRENACORE -DUART3MHZ -DGENSRAM -DINFERRED_SRAM $(SIRENA_DEFS)

sirena.vvp: sirena.v sirenacore.v sirena_test.v icucore.v \
 evgen.v floats.v \
 frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
 frontend_test.v  fifo8_sim.v serializer.v \
 heteptcore.v backend.v opheater.v \
 message.v uart.v crc.v \
 msg_regs.v ppsschedule.v l3code.v hamming.v \
 ppsschedule.hex memport.v eeprom.v \
 compression.v encode.v itof.v log2by8.v \
 processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v \
 adderi.v mult.v bitrange.v \
 mem.v l3registerfile.v counters.v fifo.v pha.v \
 ept.l3v no_het.l3v por.v

QUARTUS=/usr/local/quartus/altera13.1/quartus
export PATH:=$(PATH):$(QUARTUS)/bin

QDIR=quartus
$(QDIR)/%.rbf: %.qpf %.qsf %.sdc
	quartus_map $<
	quartus_fit $<
	quartus_asm $<
	quartus_sta $<
	grep -i warning $(QDIR)/$*.*.rpt > $*.warnings

FRONTEND = conf_reg.v spi_slave.v pll96.v spififo.v frontend.v packetfifo.v

SIRENA_SOURCES = sirena.v \
 sirenacore.v sirena_test.v \
 evgen.v floats.v \
 frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v \
 frontend_test.v  fifo8_sim.v \
 heteptcore.v backend.v opheater.v \
 message.v uart.v crc.v \
 msg_regs.v ppsschedule.v l3code.v hamming.v \
 ppsschedule.hex memport.v eeprom.v \
 compression.v encode.v itof.v \
 processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v \
 adderi.v mult.v bitrange.v \
 mem.v l3registerfile.v counters.v fifo.v pha.v

SPW_SOURCES = spwirena_core.v SpW.v serializer.v 

$(QDIR)/sirena.rbf: $(SIRENA_SOURCES)
$(QDIR)/sirena_ce4.rbf: $(SIRENA_SOURCES)
$(QDIR)/icucore.rbf: sirena.v $(FRONTEND) 
$(QDIR)/spwsirena.rbf: $(SIRENA_SOURCES) $(SPW_SOURCES)
$(QDIR)/sirenaspw.rbf: $(SIRENA_SOURCES) $(SPW_SOURCES)

uart.vvp: uart.v fifo8_sim.v
uart_FLAGS = -DUART_TEST -DALTERA_FIFO8 $(UART_DEFS) -s uart_test

MESSAGE_FIFO = fifo.v hamming.v mem.v
# MESSAGE_FIFO =  fifo8_sim.v
message.vvp: message.v crc.v uart.v $(MESSAGE_FIFO)
message_FLAGS = -DMESSAGE_TEST -DINFERRED_SRAM -s message_test
SpW_message.vvp: message.v crc.v uart.v SpW.v serializer.v
SpW_message_FLAGS = -DMESSAGE_TEST -DCCSDS_APID="11'h666" -s SpW_message_test

memory_FLAGS = -DMEMORY_TEST -s memory_test

l3registerfile.vvp: l3registerfile.v hamming.v mem.v
l3registerfile_FLAGS = -DL3REG_TEST -s l3registerfile_test -DINFERRED_SRAM

l3code.vvp: l3code.v hamming.v message.v uart.v crc.v fifo.v
l3code_FLAGS =  -DL3CODE_TEST -s l3code_test -DINFERRED_SRAM

hkspi_FLAGS = -DHKSPI_TEST -s hkspi_test

fifo.vvp: fifo.v hamming.v mem.v
fifo_FLAGS = -DFIFO_TEST -s fifo_test -DINFERRED_SRAM

MEM=CE4
memport_FLAGS = -DMEMPORT_TEST -DM24MHZ -DMEM_$(MEM) -DINFERRED_SRAM -s memport_test
memport.vvp: memport.v hamming.v eeprom.v mem.v

backend_FLAGS = -DBACKEND_TEST -s backend_test
l3win_FLAGS = -s l3win_test -DM24MHZ
ifeq ($(RAM_ACTEL),No)
  RAMS=mem.v 
  backend_FLAGS += -DINFERRED_SRAM
  l3win_FLAGS += -DINFERRED_SRAM
else
  RAMS=mem.v \
	RAM64K36_sim.v memWxActel.v mem36x128.v mem36x512.v mem72x128.v mem72x256.v \
	mem36x2048.v mem72x1024.v mem72x2048.v mem72x512.v \
	mem36x1024.v mem36x256.v
  backend_FLAGS += -DTARGET_ACTEL
  l3win_FLAGS += -DTARGET_ACTEL
endif

backend.vvp: backend.v hamming.v l3code.v l3registerfile.v ppsschedule.v memport.v fifo.v \
	message.v pha.v eeprom.v msg_regs.v counters.v $(RAMS) \
        compression.v encode.v itof.v log2by8.v \
	processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v adderi.v mult.v bitrange.v \
	test.l3v

l3win.vvp: l3win_test.v backend.v hamming.v l3code.v l3registerfile.v ppsschedule.v memport.v fifo.v \
	message.v pha.v eeprom.v msg_regs.v counters.v $(RAMS) \
        compression.v encode.v itof.v log2by8.v \
	processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v adderi.v mult.v bitrange.v \
	ept.l3v ept_dps.iv

L3TEST_UNIT = STEP
l3test_FLAGS = -s l3test -DM24MHZ -DINFERRED_SRAM -D$(L3TEST_UNIT)_PHA

l3test.vvp: l3test.v backend.v hamming.v l3code.v l3registerfile.v ppsschedule.v memport.v fifo.v \
	message.v pha.v eeprom.v msg_regs.v counters.v $(RAMS) \
        compression.v encode.v itof.v log2by8.v \
	processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v adderi.v mult.v bitrange.v \
	l3test.l3v l3test.ev stein_pha.v countbits.v

mult.vvp: mult.v
mult_FLAGS = -DMULT_TEST

l3regfifo_FLAGS = -DL3REGFIFO_TEST -s fifo_tb

processor.vvp: processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v adderi.v mult.v bitrange.v
processor_FLAGS = -DPROCESSOR_TEST -s processor_test

L3C = l3/l3.py
L3DIS = l3/l3dis.py
%.l3c: %.l3 $(L3C) .%.forward
	$(L3C) -g hex -o $@ $<
%.l3v: %.l3 $(L3C) .%.forward
	$(L3C) -g verilog -vv -o $@ -l $*.l3d $<
%.l3py: %.l3 $(L3C) .%.forward
	$(L3C) -g python -vv -o $@ -l $*.l3d $<
.%.forward: %.l3 $(L3C) 
	$(L3C) -g hex -o /dev/null $<
	touch $@

.ept.forward: hetept_config.l3 hetept_pha.l3 ept_calib.l3
.step.forward: step_config.l3 step_pha.l3 step_calib.l3

%.l3dis: %.l3c $(L3DIS)
	$(L3DIS) -F 'R%(addr)-3d= %(cond)-3s %(mnem)-5s %(args)-25s # 0x%(instr)08x' $< > $@

%.l3cc: %.l3dis
	$(L3C) -g hex -o $@ $<
	-diff -u $*.l3c $*.l3cc

clean:
	rm -f *.l3[cdv] *.l3dis *.l3cc .*.forward *.vvp

pps_gen_FLAGS = -DPPS_GEN_TEST -s pps_gen_test
pps_gen.vvp: icucore.v

$(QDIR)/icucore.rbf: sirena.v icucore.v $(FRONTEND) memory.v uart.v secondcyclone.v

itof_FLAGS =  -DITOF_TEST -s itof_test
itof.vvp: itof.v

crc_FLAGS = -DCRC_TEST
crc.vvp: crc.v

s72_test.vvp: hamming.v
s72_test_FLAGS = -DS72_TEST -s s72_test
s18_test.vvp: hamming.v
s18_test_FLAGS = -DS18_TEST -s s18_test
s56_test.vvp: hamming.v
s56_test_FLAGS = -DS56_TEST -s s56_test
s64_test.vvp: hamming.v
s64_test_FLAGS = -DS64_TEST -s s64_test

evgen.vvp: evgen.v crc.v floats.v
evgen_FLAGS = -DEVGEN_TEST -s evgen_test

uf.vvp: floats.v 
uf_FLAGS = -DUF_TEST -s uf_test

log2by8.vvp: log2by8.v
log2by8_FLAGS = -DLOG2BY8_TEST -s log2by8_test

encschedule.vvp: compression.v encode.v ppsschedule.v
encschedule_FLAGS = -DENCSCHEDULE_TEST -s encschedule_test

counters.vvp: counters.v mem.v hamming.v pha.v itof.v
counters_FLAGS = -s counters_test -DCOUNTERS_TEST -DINFERRED_SRAM

sirenacntr_FLAGS = -s sirenacntr_test -DSIRENACNTR -DSIRENACNTR_TEST \
   -DINFERRED_SRAM
sirenacntr.vvp: sirenacntr.v  memport.v \
 frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
 frontend_test.v  fifo8_sim.v serializer.v nmcounter.v mem.v

$(QDIR)/sirenacntr.rbf:  sirenacntr.v memport.v \
 frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
 nmcounter.v mem.v

baudgen.vvp: baudgen_test.v uart.v
baudgen_FLAGS = -s baudgen_test

encode_FLAGS = -DENCODE_TEST -s encode_test
encode.vvp: encode.v

mem_sqi_FLAGS = -DMEM_SQI_TEST -s mem_ifc_test
mem_sqi.vvp: memport.v