quartus/spwsirena.fit.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/spwsirena.fit.rpt:Warning (15901): PLL "pll384:pll0|altpll:altpll_component|altpll_r273:auto_generated|pll1" has parameter clk0_counter set to C0 specified but port CLK[0] is not connected
quartus/spwsirena.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
quartus/spwsirena.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
quartus/spwsirena.fit.rpt:Warning (176674): Following 7 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
quartus/spwsirena.fit.rpt: Warning (176118): Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)"
quartus/spwsirena.fit.rpt: Warning (176118): Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)"
quartus/spwsirena.fit.rpt: Warning (176118): Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)"
quartus/spwsirena.fit.rpt: Warning (176118): Pin "FE_clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "FE_clk(n)"
quartus/spwsirena.fit.rpt: Warning (176118): Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
quartus/spwsirena.fit.rpt: Warning (176118): Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
quartus/spwsirena.fit.rpt: Warning (176118): Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
quartus/spwsirena.fit.rpt:Warning (176250): Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/spwsirena.fit.rpt:Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
quartus/spwsirena.fit.rpt:Warning (169064): Following 24 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
quartus/spwsirena.map.rpt:; errsum ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/spwsirena.map.rpt:; almost_full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/spwsirena.map.rpt:; halffull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/spwsirena.map.rpt:; fifo_empty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/spwsirena.map.rpt:; c2 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/spwsirena.map.rpt:; c4 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/spwsirena.map.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
quartus/spwsirena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/serializer.v(188)
quartus/spwsirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at spwirena_core.v(88): Parameter Declaration in module "spwirena_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/spwsirena.map.rpt:Warning (10034): Output port "sram_a" at sirena.v(13) has no driver
quartus/spwsirena.map.rpt:Warning (10034): Output port "sram_ce" at sirena.v(15) has no driver
quartus/spwsirena.map.rpt:Warning (10034): Output port "debug" at sirena.v(26) has no driver
quartus/spwsirena.map.rpt:Warning (10034): Output port "sram_we" at sirena.v(16) has no driver
quartus/spwsirena.map.rpt:Warning (10034): Output port "sram_oe" at sirena.v(17) has no driver
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(97): truncated value with size 32 to match size of target (4)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(254): truncated value with size 32 to match size of target (8)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(256): truncated value with size 32 to match size of target (8)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(70): truncated value with size 32 to match size of target (3)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(150): truncated value with size 32 to match size of target (10)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(171): truncated value with size 32 to match size of target (10)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (5)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (10)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(111): truncated value with size 32 to match size of target (15)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(127): truncated value with size 32 to match size of target (9)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(132): truncated value with size 32 to match size of target (9)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(147): truncated value with size 32 to match size of target (10)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(165): truncated value with size 32 to match size of target (16)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(315): truncated value with size 32 to match size of target (8)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(509): truncated value with size 32 to match size of target (8)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(526): truncated value with size 32 to match size of target (8)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(527): truncated value with size 32 to match size of target (4)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(584): truncated value with size 32 to match size of target (12)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(593): truncated value with size 32 to match size of target (12)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(595): truncated value with size 32 to match size of target (3)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(606): truncated value with size 32 to match size of target (12)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(622): truncated value with size 32 to match size of target (12)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(246): truncated value with size 4 to match size of target (3)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(248): truncated value with size 32 to match size of target (3)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(296): truncated value with size 32 to match size of target (4)
quartus/spwsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(397): truncated value with size 32 to match size of target (8)
quartus/spwsirena.map.rpt:Warning (14284): Synthesized away the following node(s):
quartus/spwsirena.map.rpt: Warning (14285): Synthesized away the following RAM node(s):
quartus/spwsirena.map.rpt:Warning (12241): 5 hierarchies have connectivity warnings - see the Connectivity Checks report folder
quartus/spwsirena.map.rpt:Warning (13039): The following bidir pins have no drivers
quartus/spwsirena.map.rpt: Warning (13040): Bidir "sram_d[0]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "sram_d[1]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "sram_d[2]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "sram_d[3]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "sram_d[4]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "sram_d[5]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "sram_d[6]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "sram_d[7]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "FE_port[0]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "FE_port[1]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "FE_port[2]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "FE_port[3]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "FE_port[4]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "FE_port[5]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "FE_port[6]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "FE_port[7]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "FE_port[8]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "FE_port[9]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "FE_port[10]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "FE_port[11]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "FE_port[12]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "FE_port[13]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "FE_port[14]" has no driver
quartus/spwsirena.map.rpt: Warning (13040): Bidir "FE_port[15]" has no driver
quartus/spwsirena.map.rpt:Warning (13024): Output pins are stuck at VCC or GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[0]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[1]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[2]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[3]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[4]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[5]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[6]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[7]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[8]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[9]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[10]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[11]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[12]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[13]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[14]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[15]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[16]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[17]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[18]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[19]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_a[20]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_ce[2]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_ce[1]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_we" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "sram_oe" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "debug[6]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "debug[5]" is stuck at GND
quartus/spwsirena.map.rpt: Warning (13410): Pin "debug[4]" is stuck at GND
quartus/spwsirena.map.rpt:Warning (15901): PLL "pll384:pll0|altpll:altpll_component|altpll_r273:auto_generated|pll1" has parameter clk0_counter set to C0 specified but port CLK[0] is not connected
quartus/spwsirena.map.rpt:Warning (21074): Design contains 5 input pin(s) that do not drive logic
quartus/spwsirena.map.rpt: Warning (15610): No output dependent on input pin "clk_T1"
quartus/spwsirena.map.rpt: Warning (15610): No output dependent on input pin "trigger"
quartus/spwsirena.map.rpt: Warning (15610): No output dependent on input pin "Rx[2]"
quartus/spwsirena.map.rpt: Warning (15610): No output dependent on input pin "Rx[1]"
quartus/spwsirena.map.rpt: Warning (15610): No output dependent on input pin "FE_clk"
