110 lines
12 KiB
Text
110 lines
12 KiB
Text
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ccdsirena.asm.rpt:Info: Quartus II Assembler was successful. 0 errors, 0 warnings
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ccdsirena.fit.rpt: 5. I/O Assignment Warnings
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ccdsirena.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
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ccdsirena.fit.rpt:; I/O Assignment Warnings ;
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ccdsirena.fit.rpt:Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.
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ccdsirena.fit.rpt:Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
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ccdsirena.fit.rpt:Warning: Following 7 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
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ccdsirena.fit.rpt: Warning: Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)"
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ccdsirena.fit.rpt: Warning: Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)"
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ccdsirena.fit.rpt: Warning: Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)"
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ccdsirena.fit.rpt: Warning: Pin "FE_clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "FE_clk(n)"
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ccdsirena.fit.rpt: Warning: Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
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ccdsirena.fit.rpt: Warning: Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
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ccdsirena.fit.rpt: Warning: Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
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ccdsirena.fit.rpt:Warning: Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
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ccdsirena.fit.rpt:Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
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ccdsirena.fit.rpt:Warning: Following 24 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
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ccdsirena.fit.rpt:Info: Quartus II Fitter was successful. 0 errors, 13 warnings
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ccdsirena.map.rpt:; rbi ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
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ccdsirena.map.rpt:; halffull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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ccdsirena.map.rpt:; c1 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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ccdsirena.map.rpt:; c2 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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ccdsirena.map.rpt:; c3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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ccdsirena.map.rpt:; c4 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdsirena.v(126): truncated value with size 32 to match size of target (8)
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ccdsirena.map.rpt:Warning (10034): Output port "debug" at ccdsirena.v(34) has no driver
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(101): truncated value with size 32 to match size of target (4)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(259): truncated value with size 32 to match size of target (8)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(261): truncated value with size 32 to match size of target (8)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(83): truncated value with size 32 to match size of target (3)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(137): truncated value with size 32 to match size of target (10)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(65): truncated value with size 32 to match size of target (4)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(120): truncated value with size 32 to match size of target (9)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(179): truncated value with size 32 to match size of target (12)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(202): truncated value with size 32 to match size of target (6)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(214): truncated value with size 32 to match size of target (12)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(242): truncated value with size 32 to match size of target (6)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(253): truncated value with size 32 to match size of target (12)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(258): truncated value with size 32 to match size of target (3)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(275): truncated value with size 32 to match size of target (8)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(292): truncated value with size 32 to match size of target (5)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(313): truncated value with size 32 to match size of target (8)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(324): truncated value with size 32 to match size of target (8)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(336): truncated value with size 32 to match size of target (8)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(347): truncated value with size 32 to match size of target (8)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(408): truncated value with size 32 to match size of target (16)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(450): truncated value with size 32 to match size of target (4)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(461): truncated value with size 32 to match size of target (6)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(472): truncated value with size 32 to match size of target (12)
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ccdsirena.map.rpt:Warning (10230): Verilog HDL assignment warning at ccdclocks.v(534): truncated value with size 32 to match size of target (16)
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ccdsirena.map.rpt:Warning: 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
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ccdsirena.map.rpt:Warning: The following bidir pins have no drivers
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ccdsirena.map.rpt: Warning: Bidir "FE_port[0]" has no driver
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ccdsirena.map.rpt: Warning: Bidir "FE_port[1]" has no driver
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ccdsirena.map.rpt: Warning: Bidir "FE_port[2]" has no driver
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ccdsirena.map.rpt: Warning: Bidir "FE_port[3]" has no driver
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ccdsirena.map.rpt: Warning: Bidir "FE_port[4]" has no driver
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ccdsirena.map.rpt: Warning: Bidir "FE_port[5]" has no driver
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ccdsirena.map.rpt: Warning: Bidir "FE_port[6]" has no driver
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ccdsirena.map.rpt: Warning: Bidir "FE_port[7]" has no driver
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ccdsirena.map.rpt: Warning: Bidir "FE_port[8]" has no driver
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ccdsirena.map.rpt: Warning: Bidir "FE_port[9]" has no driver
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ccdsirena.map.rpt: Warning: Bidir "FE_port[10]" has no driver
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ccdsirena.map.rpt: Warning: Bidir "FE_port[11]" has no driver
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ccdsirena.map.rpt: Warning: Bidir "FE_port[12]" has no driver
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ccdsirena.map.rpt: Warning: Bidir "FE_port[13]" has no driver
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ccdsirena.map.rpt: Warning: Bidir "FE_port[14]" has no driver
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ccdsirena.map.rpt: Warning: Bidir "FE_port[15]" has no driver
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ccdsirena.map.rpt:Warning: Output pins are stuck at VCC or GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[0]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[1]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[2]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[3]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[4]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[5]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[6]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[7]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[8]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[9]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[10]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[11]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[12]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[13]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[14]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[15]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[16]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[17]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[18]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[19]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_a[20]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_ce[2]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "sram_ce[1]" is stuck at VCC
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ccdsirena.map.rpt: Warning (13410): Pin "sram_oe" is stuck at VCC
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ccdsirena.map.rpt: Warning (13410): Pin "sram_we" is stuck at VCC
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ccdsirena.map.rpt: Warning (13410): Pin "debug[6]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "debug[5]" is stuck at GND
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ccdsirena.map.rpt: Warning (13410): Pin "debug[4]" is stuck at GND
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ccdsirena.map.rpt:Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
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ccdsirena.map.rpt:Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
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ccdsirena.map.rpt:Warning: Design contains 7 input pin(s) that do not drive logic
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ccdsirena.map.rpt: Warning (15610): No output dependent on input pin "clk_T1"
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ccdsirena.map.rpt: Warning (15610): No output dependent on input pin "trigger"
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ccdsirena.map.rpt: Warning (15610): No output dependent on input pin "Rx[4]"
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ccdsirena.map.rpt: Warning (15610): No output dependent on input pin "Rx[3]"
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ccdsirena.map.rpt: Warning (15610): No output dependent on input pin "Rx[2]"
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ccdsirena.map.rpt: Warning (15610): No output dependent on input pin "Rx[1]"
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ccdsirena.map.rpt: Warning (15610): No output dependent on input pin "FE_clk"
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ccdsirena.map.rpt:Info: Quartus II Analysis & Synthesis was successful. 0 errors, 84 warnings
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ccdsirena.sta.rpt:Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings
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