solo_altera/erena/altera/Makefile

VERILOG=/usr/local/bin/iverilog
#VERILOG=/usr/bin/iverilog

VERILOGFLAGS = -v -DSIMULATION $($*_FLAGS)
%.vvp:
	$(VERILOG) $(VERILOGFLAGS) -o $@ $^

vcd/%.lxt: %.vvp
	$< -lxt2 | tee $*.log

.PRECIOUS: vcd/%.lxt

VPATH=../../altera:../../altera/mega:../../arena/altera:../../irena/altera/adc128:../../irena/altera:../../nm64/altera

erena_FILES = erena.v erena_test.v pulser.v serializer.v ad9649.v \
 frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
 frontend_test.v oscilloscope.v  spi_master_adc.v \
 epipe.v ad9251_data.v ms5540c.v

erena_FLAGS = -DERENA_EPIPE -s erena_test
erena.vvp: $(erena_FILES)

erenasc_FLAGS = -DERENA_EPIPE -DNM64_PRIM -DADC40MHz -DEPULSER -s erena_test
erenasc.vvp: $(erena_FILES) ltc2656.v ads8688.v epulser.v

QUARTUS=/usr/local/quartus/altera13.1/quartus
export PATH:=$(PATH):$(QUARTUS)/bin

MAPFLGS = $(patsubst %, --verilog_macro="%",$($*_MAPDEFS) $(MAPDEFS))
erena_MAPDEFS = ERENA_EPIPE=1

quartus/%.rbf: %.qpf %.qsf %.sdc
	quartus_map $< $(MAPFLGS)
	quartus_fit $<
	quartus_asm $<
	quartus_sta $<
	grep -i warning quartus/$*.*.rpt > $*.warnings

erena_SYNTH_FILES = erena.v conf_reg.v spi_slave.v pll240.vhd spififo.v frontend.v packetfifo.v \
   ad9649.v spi_master_adc.v epipe.v ms5540c.v countbits.v

quartus/erena.rbf: $(erena_SYNTH_FILES)
quartus/erenasc.rbf: $(erena_SYNTH_FILES) ltc2656.v ads8688.v

epipe.vvp: epipe.v conf_reg.v pulser.v spififo_sim.v
epipe_FLAGS = -DEPIPE_TEST -s epipe_test