solo_altera/irena/altera/Makefile

VERILOG=/usr/local/bin/iverilog
#VERILOG=/usr/bin/iverilog

VERILOGFLAGS = -v -DSIMULATION $($*_FLAGS)
%.vvp: %.v
	$(VERILOG) $(VERILOGFLAGS) -o $@ $^

vcd/%.fst: %.vvp
	$< -fst | tee $*.log

.PRECIOUS: vcd/%.lxt

VPATH=.:./direna:./adc128:../../altera:../../altera/mega:../../nm64/altera:../../sirena/altera

irena.vvp: irena_test.v frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v \
	   countbits.v ms5540c.v \
           direna.v direna_test.v direna_adc.v \
           adccntl.v filter.v trigger.v triggeror.v

irena_core.vvp: irena.v irena_test.v \
           frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v \
	   countbits.v ms5540c.v nmcounter.v mem.v \
           direna.v direna_test.v direna_adc.v \
           adccntl.v filter.v \
           irena_core.v sfilter.v itof.v \
	   hamming.v

irena_FLAGS = -sdirena_adc -DADC_SAMPLE_EARLY -DDIRENA_TEST -DDIRENACORE

OPT=-DDD48
irena_core_FLAGS = -sdirena_adc -DADC_SAMPLE_EARLY -DDIRENA_TEST $(OPT) \
                   -DIRENACORE -DHAVE_ABT2F -DAD7276 -DGENSRAM -DINFERRED_SRAM -DMEMSR_EDAC

QUARTUS=/usr/local/quartus/altera13.1/quartus
export PATH:=$(PATH):$(QUARTUS)/bin

MAPFLGS = $(patsubst %, --verilog_macro="%",$($*_MAPDEFS))

QDIR=quartus

$(QDIR)/%.rbf: %.qpf %.qsf %.sdc \
       frontend.v spi_slave.v conf_reg.v packetfifo.v spififo.v
	quartus_map $< $(MAPFLGS)
	quartus_fit $<
	quartus_asm $<
	quartus_sta $<
	grep -i warning $(QDIR)/$*.*.rpt > $*.warnings

ADC_SAMPLE_EARLY = ADC_SAMPLE_EARLY=1
ifeq ($(ESTHER),1)
 DISABLE = 00 01 02 03 04 05 06 07 08 09 10 11       14 15 16 17
irena_MAPDEFS = $(ADC_SAMPLE_EARLY) \
  $(patsubst %,DIS%=1,$(DISABLE)) \
  SHORT_PACKETS=03000
  irena_FLAGS += -DSHORT_PACKETS=03000
else
irena_MAPDEFS = $(ADC_SAMPLE_EARLY)
endif

$(QDIR)/irena.rbf: irena.v countbits.v ms5540c.v \
           direna.v adccntl.v filter.v trigger.v triggeror.v \
	   sram.v sram1024x32.v pll96.v mul13x13.v 

ms5540c_FLAGS =  -sms5540c_test  -DMS5540C_TEST
ms5540c.vvp: ms5540c.v countbits.v

$(QDIR)/irena2.rbf:
	rm -f irena.rbf
	$(MAKE) ESTHER=1 irena.rbf
	mv irena.rbf irena2.rbf
	mv irena.warnings irena2.warnings 

$(QDIR)/irenacore.rbf: irena.v countbits.v ms5540c.v nmcounter.v \
           direna.v adccntl.v filter.v \
	   irena_core.v sfilter.v itof.v \
	   sram.v sram1024x32.v pll96.v mul13x13.v 

irenacore2thr.qpf irenacore2thr.qsf irenacore2thr.sdc: irenacore2thr.%: irenacore.%
	cp -v $< $@

$(QDIR)/irenacore2thr.rbf: irena.v countbits.v ms5540c.v nmcounter.v \
           direna.v adccntl.v filter.v \
	   irena_core.v sfilter.v itof.v \
	   sram.v sram1024x32.v pll96.v mul13x13.v 

irenacore2thr_MAPDEFS = TWOTHR=1

irena48.qpf irena48.qsf irena48.sdc: irena48.%: irenacore.%
	cp -v $< $@

$(QDIR)/irena48.rbf: irena.v countbits.v ms5540c.v nmcounter.v \
           direna.v adccntl.v filter.v \
	   irena_core.v sfilter.v itof.v \
	   sram.v sram1024x32.v pll96.v mul13x13.v 

irena48_MAPDEFS = DD48=1

$(QDIR)/i128.rbf: i128.v sfilter.v

i128_FLAGS = -DAD7276 -DGENSRAM
i128.vvp: i128.v sfilter.v \
  pulser.v frontend_test.v \
  bitcount.v ms5540c.v \
  frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v