Stephan/solo_altera
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188 commits

Author SHA1 Message Date
stephan
62db8906c1 spi_slave: fix ssel ?! 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7941 bc5caf13-1734-44f8-af43-603852e9ee25
 2020-03-01 22:50:57 +00:00
stephan
a14ac60d2c nm_mcs: seems to work 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7920 bc5caf13-1734-44f8-af43-603852e9ee25
 2020-02-18 20:49:23 +00:00
stephan
5af870a7b8 nm_mcs: sim and synthesis 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7918 bc5caf13-1734-44f8-af43-603852e9ee25
 2020-02-18 04:46:31 +00:00
stephan
500bf34ac9 new nmrena usage: nm_mcs 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7916 bc5caf13-1734-44f8-af43-603852e9ee25
 2020-02-17 19:32:23 +00:00
stephan
7003596b62 frontend: add register conf3 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7857 bc5caf13-1734-44f8-af43-603852e9ee25
 2019-12-04 23:02:36 +00:00
stephan
1265b68243 SpW: 
bit timeout
    FIX:  this logic required max 850ns between @(posedge sclk) 
          The standard allows 850ns between bits, i.e., 1700ns
          between bit pairs.  Now it allows for 1700ns.
    Nonconformance: In case of skewed dutycycle in the sclk, bit 
    times longer than 850ns will not be detected, as long as two 
    bits arrive in 1700ns.  That is very unlikely to be a problem.


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7847 bc5caf13-1734-44f8-af43-603852e9ee25
 2019-11-24 20:52:55 +00:00
stephan
40d4c83b8f comment typo 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7744 bc5caf13-1734-44f8-af43-603852e9ee25
 2019-10-15 18:25:20 +00:00
stephan
4b65d071cd alt/scan[2] 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7584 bc5caf13-1734-44f8-af43-603852e9ee25
 2019-07-02 22:48:43 +00:00
stephan
485b549792 nmhertz: nmrena without nm 
up to three DACs and ADCs
	and a new scan generator


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7541 bc5caf13-1734-44f8-af43-603852e9ee25
 2019-05-26 22:49:35 +00:00
stephan
6cf1db9a0b SpW3 gold 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7378 bc5caf13-1734-44f8-af43-603852e9ee25
 2019-03-21 21:38:29 +00:00
stephan
6553ac07bb SpW: fix bit timeout while init. 
When an rx bit timeout happens while init=1, the init stays asserted until
   the next sclk.  We need to flag that case to do the idle<=0 transition and
   to properly count bits of the leading NULL.



git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7370 bc5caf13-1734-44f8-af43-603852e9ee25
 2019-03-19 18:53:39 +00:00
terasa
3f026cdeba SpW.v: Add testcase for init/idle pingpong error. 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7368 bc5caf13-1734-44f8-af43-603852e9ee25
 2019-03-19 16:11:32 +00:00
stephan
037d6aea0f SpW: fix subtrahend length in delayc 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7262 bc5caf13-1734-44f8-af43-603852e9ee25
 2019-02-04 11:14:23 +00:00
stephan
efff3d7c17 SpW: gold for EEP/EoP fix 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7251 bc5caf13-1734-44f8-af43-603852e9ee25
 2019-01-28 16:53:34 +00:00
stephan
ce21c50c1d altera/SpW.v: Fix Rx EOP/EEP. 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7250 bc5caf13-1734-44f8-af43-603852e9ee25
 2019-01-28 16:24:36 +00:00
terasa
9ffdb045e1 altera/SpW.v: Fix Tx EOP/EEP. 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7249 bc5caf13-1734-44f8-af43-603852e9ee25
 2019-01-28 16:16:19 +00:00
stephan
b41fc7daef hetept por: self init message 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7111 bc5caf13-1734-44f8-af43-603852e9ee25
 2018-11-21 14:36:11 +00:00
stephan
6a682cb32f Warning (10463): Verilog HDL Declaration warning at SpW.v(42): "bit" is SystemVerilog-2005 keyword 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7073 bc5caf13-1734-44f8-af43-603852e9ee25
 2018-11-02 20:58:45 +00:00
stephan
faa51b4a1f frontend: add .wp() to reset_reg, reset all when wp==0 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@6231 bc5caf13-1734-44f8-af43-603852e9ee25
 2017-08-30 17:00:39 +00:00
stephan
3c1d388e2d ltc2656: let's remove that NOP business, now that we have a pipe 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@6218 bc5caf13-1734-44f8-af43-603852e9ee25
 2017-08-28 13:17:07 +00:00
stephan
0d76c95583 nmrena: add uarts 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@6208 bc5caf13-1734-44f8-af43-603852e9ee25
 2017-08-23 20:57:41 +00:00
stephan
63b087b112 nmrena: uart implementation, just typed in, no testing 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@6201 bc5caf13-1734-44f8-af43-603852e9ee25
 2017-08-22 22:39:15 +00:00
stephan
55b67fd076 merge C'E4 tuning into trunc 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5958 bc5caf13-1734-44f8-af43-603852e9ee25
 2017-03-17 20:56:45 +00:00
stephan
b8ac17d866 secondcyclone: add port ser_master_rx.rxs_valid() as link active indicator 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5945 bc5caf13-1734-44f8-af43-603852e9ee25
 2017-03-15 16:32:03 +00:00
stephan
c22f245431 serializer: old gold 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5944 bc5caf13-1734-44f8-af43-603852e9ee25
 2017-03-15 16:29:07 +00:00
stephan
9577733840 serializer: very old gold 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5943 bc5caf13-1734-44f8-af43-603852e9ee25
 2017-03-15 16:28:17 +00:00
stephan
5f13437017 C'E4 ana,dig/v01: merge periphery fixes into trunc 
MM   altera/actel/actel.v
   MM   change4/altera/ce4ana.v
   R  + flyrena/altera/ce4dig.v
   MM   hetept/altera/heteptana.v

   Merged /solo/eda/change4/dig/v01/altera/actel/actel.v:r5814,5837
   Merged /solo/eda/change4/ana/v01/ce4ana.v:r5845-5846
   Reverse-merged /solo/eda/heteptdig/em/v01/heteptdig.v:r2217
   Reverse-merged /solo/eda/heteptdig/em/v03/heteptdig.v:r2651
   Reverse-merged /solo/eda/heteptdig/em/v04/heteptdig.v:r2703
   Reverse-merged /solo/eda/heteptdig/em/v05/heteptdig.v:r3330-3350,3357,3361,3367-3368
   Reverse-merged /solo/eda/heteptdig/em/v06/heteptdig.v:r3540,3604
   Reverse-merged /solo/eda/heteptdig/em/v08/heteptdig.v:r3885
   Merged /solo/eda/flyrena/altera/heteptdig.v:r2125,2204,2207,2212,2219,2319-2323,2408,2563,2591,3009,3186,3355,3378,3380,3390,3507,3549,3875,3904,3956,3978,4029,4355
   Merged /solo/eda/change4/ana/v01/heteptana.v:r5832



git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5942 bc5caf13-1734-44f8-af43-603852e9ee25
 2017-03-15 13:03:28 +00:00
stephan
96a79f1bec packetfifo: pipeline mask bit count more agressively 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5869 bc5caf13-1734-44f8-af43-603852e9ee25
 2017-02-18 00:11:02 +00:00
stephan
55d2f055a1 spw_sologse: tweaks for f2 timing, ARxC 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5866 bc5caf13-1734-44f8-af43-603852e9ee25
 2017-02-17 23:09:08 +00:00
stephan
6dd01df1c0 spififo: add parameter ALMOST 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5863 bc5caf13-1734-44f8-af43-603852e9ee25
 2017-02-17 19:57:36 +00:00
stephan
13742c4e0e swirena: fixes and core2(disbaled) 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5860 bc5caf13-1734-44f8-af43-603852e9ee25
 2017-02-17 13:14:46 +00:00
stephan
004265056a spwirena: feature complete, simulation 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5858 bc5caf13-1734-44f8-af43-603852e9ee25
 2017-02-17 01:07:48 +00:00
stephan
5dc1cf81d9 countbits: balanced adder tree implementation, quartus is much happier 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5704 bc5caf13-1734-44f8-af43-603852e9ee25
 2016-12-06 21:11:04 +00:00
stephan
47789acefd mega: lvds io buffer 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5688 bc5caf13-1734-44f8-af43-603852e9ee25
 2016-11-30 13:21:35 +00:00
stephan
392cb0374c SpW: harden for sim startup without reset 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5664 bc5caf13-1734-44f8-af43-603852e9ee25
 2016-11-23 23:53:09 +00:00
stephan
179ac031d0 SpW: serialize EOP with nChar, i.e., feed EOP through nchar_req, level3 simulation 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5660 bc5caf13-1734-44f8-af43-603852e9ee25
 2016-11-23 13:24:50 +00:00
stephan
3df8eb2317 SpW: third level 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5659 bc5caf13-1734-44f8-af43-603852e9ee25
 2016-11-22 19:57:09 +00:00
stephan
487e347465 SpW: fix parity 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5654 bc5caf13-1734-44f8-af43-603852e9ee25
 2016-11-21 23:22:47 +00:00
stephan
5465141aea SpW 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5648 bc5caf13-1734-44f8-af43-603852e9ee25
 2016-11-21 00:36:54 +00:00
stephan
ce2cbb6561 sfilter dout_pipe: sample DCLK to find propper tick phase 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5476 bc5caf13-1734-44f8-af43-603852e9ee25
 2016-10-03 10:19:49 +00:00
stephan
3d67afe02c fpgas: add module por: Power On Reset 
por is treated as abort
	por resets the opheater

	There is a 1 in 256 chance that the por will not happen
	if registers initialize randomly at power on.


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@4152 bc5caf13-1734-44f8-af43-603852e9ee25
 2015-04-12 19:47:48 +00:00
stephan
919e873cc6 sirena: with eeprom in RAM 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@4030 bc5caf13-1734-44f8-af43-603852e9ee25
 2015-03-24 23:33:54 +00:00
stephan
245160eec5 verilog: fix more nonblocking assignments 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3971 bc5caf13-1734-44f8-af43-603852e9ee25
 2015-03-18 01:00:31 +00:00
stephan
d4343bb384 heteptana: altera bitfile 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3921 bc5caf13-1734-44f8-af43-603852e9ee25
 2015-03-10 21:37:36 +00:00
stephan
9591b2d56b serializer: fix deserializer clcok transition phase 
The data was supposed to go from sclk to mclk on the rising
	edge of token[7].  It was using the falling edge instead.
	This worked well, because all past applications had a fixed 
	phase between sclk and mclk (and mclk<=sclk).  The rpigse 
	receives data from a solo unit, and here the phase where
	out[] is transfered into data[] drifts through the token[] edge, 
	such that at certain phases the cmd and invert bits are 
	taken from different words, and thus produce a long stream
	of bogus data_e.  

	The fack that mclk>sclk in the rpigse case probably does not 
	contribute.

	This needs to be fixed even for applications with constant phase, 
	because the phase may accidently turn out to be wrong, depending on 
	temperature and other issues.


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3836 bc5caf13-1734-44f8-af43-603852e9ee25
 2015-02-19 16:02:42 +00:00
stephan
51ea20ccc6 adc128s102: merge -c 3609 from ana/em/v04: ADC IO regsiters fixes 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3713 bc5caf13-1734-44f8-af43-603852e9ee25
 2015-01-21 22:16:43 +00:00
stephan
195cc06515 itof: Fix BUG in itouf 
The exponent of the resulting float representation 
	was one less it should be.  The mantissa shift was done 
	according to the exponent in the output.

	With M=12, E=4, i.e., the standard 16-bit unsigned float, input 
	numbers up to 4095 were represented correctly.  Numbers from 
	4096..8191 were mapped to the range 0..4095.  Numbers from 8192 
	had wrong but unique representations, with one bit less in the 
	mantissa.

	This patch fixes that BUG.

	Impact: All floating point numbers from HET/EPT PQM above 
	4096 are wrong. :-(


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3678 bc5caf13-1734-44f8-af43-603852e9ee25
 2015-01-13 23:14:02 +00:00
stephan
3bcb003040 itouf: expanded test-jig 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3677 bc5caf13-1734-44f8-af43-603852e9ee25
 2015-01-13 22:47:44 +00:00
stephan
13d8d2f942 actel.v: move one directory down 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3577 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-04 10:57:12 +00:00
wetzel
432db47693 actel sim models: created file for actel specific sim models 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3572 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-02 12:15:01 +00:00