Stephan/solo_altera
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188 commits

Author SHA1 Message Date
stephan
77032048b9 packetfifo: fix match validation timing 
for the mask match case, the validation is not normally required


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3567 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-11-28 18:44:39 +00:00
stephan
d2c28a7b04 aschedule: make sure din1 ... is gated by nCS asserted 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3402 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-10-27 15:47:08 +00:00
stephan
04f4f82fcc heteptdig: merge -c 3361 from dig/em/v05 
Add ARxDD register in the IO-pad. 
	Add a mergable register in sermerge, to share with 
	the deserializer, just in case.


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3388 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-10-26 14:02:18 +00:00
stephan
a3040ddcf3 heteptdig em/v05: merge more IO timing adjustments back into the trunc. 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3351 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-10-22 19:45:53 +00:00
stephan
07ac58b101 adc128s102: merge -c 3311 from ana/em/v03 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3312 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-10-18 20:59:40 +00:00
stephan
e1dc995b49 adc128s102: add pragma synthesis, syn_preserve to inverted output 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3303 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-10-17 17:37:57 +00:00
stephan
7a5126185f adc128s102: merge -c 3298 from ana/em/v03: pragma synthesis, syn_preserve 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3302 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-10-17 17:35:01 +00:00
stephan
d87dba3619 adc128s102: add inverted adc control outputs to aschedule 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3299 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-10-17 17:21:30 +00:00
stephan
ed6a5555a6 adcschedule: 
add parameter FO=1
	for ADC control signal register replication
	to fanout to multiple IO pads with minimum delay.


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3285 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-10-16 16:39:43 +00:00
stephan
4eb5343b2a serializer: fix splitter for short low width 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2927 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-05-23 06:18:32 +00:00
stephan
ac4509d2f6 adc128s102: fix aschedule reset coinciding with mtick 
The STEIN adc controller issues a single cycle reset to the
	aschedule module after a trigger.
	When this reset coincides with an mtick, the timing of the readout
	cycle gets screwed up.  This fix resets mtick at reset.

	This patch should have no impact on HETEPT, where the reset will not
	be asserted for only a single cycle.

	This patch may not be necessary for STEIN, when the adc controller
	gets changed to not issue single cycle resets.


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2869 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-05-15 20:58:15 +00:00
stephan
33cfc8f570 packetfifo: fix bug in packet length matcher 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2738 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-04-08 18:37:26 +00:00
stephan
eca75cc94f packetfifo: add match parameter for variable size packets 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2681 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-03-27 22:49:48 +00:00
stephan
17dbc4f365 xrena frontend: revert -c -2670: quartus does not like it. 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2676 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-03-27 16:06:08 +00:00
stephan
955a973423 irena: direnacore good for irenacore transition 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2670 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-03-26 21:32:47 +00:00
wetzel
decaf8f535 removed anachronistic expression 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2639 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-03-13 14:22:37 +00:00
wetzel
b4fc73c8d7 inserted begin-ends and names for quartus compiler 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2616 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-03-06 09:50:10 +00:00
stephan
0288aea51f serializer demux: do not use 5-bit counter @ 384 MHz 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2416 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-12-20 07:03:24 +00:00
stephan
0d132b4b97 serializer split: 4x oversampling 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2413 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-12-18 10:15:38 +00:00
stephan
289256cea9 altera: PLL base clock recovery failed, use 4x oversampling at 384 MHz 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2412 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-12-17 12:02:32 +00:00
stephan
e397b63995 xrena frontend: add optional ssel input to spi_slave for RPiRENA 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2253 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-10-27 09:42:49 +00:00
stephan
5e748b9f62 hkadc: pass CLKDIV parameter to aschedule, to allow for 96MHz op in RPiRENA 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2251 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-10-27 09:40:08 +00:00
stephan
8c24c80db1 serializer: clock recovery PLL 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2236 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-10-15 16:49:09 +00:00
stephan
0ef749c9ad serializer: 
Implement a clock merged mode for 48Mbps.
  The signal provides a rising edge at 24MHz for a pll to lock on.
  In between the edges are two data bits.
  The decoder PLL must provide a clock at twice the bit rate, i.e., 96MHz.
  The encoder needs the bit clock and the data only.

  No idea if the Cyclone III PLLs can recover the clock.


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2235 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-10-15 16:47:49 +00:00
stephan
34ad834e0c ccdrena: support for recent development 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2167 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-09-16 21:25:06 +00:00
stephan
cb8df45e93 RAM64K36 SEU: reduce SEU rate by 1000 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2122 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-09-08 20:44:25 +00:00
stephan
01405b8e48 heteptdig: turn on SEU in internal RAMS 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2121 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-09-08 08:33:57 +00:00
stephan
4ac3aa3173 packed sample packets 
opheater parameter readout
SPIPE serial master states tranfer cadence parameter


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@2085 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-09-01 21:37:58 +00:00
stephan
58af81ccae move module aschedule from irena to library 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1969 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-08-12 19:23:52 +00:00
stephan
b5dc83ce32 move ADC128S102 model into the general library 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1966 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-08-12 15:16:02 +00:00
wetzel
434fc606e3 added testjig for barrel and priority-encoder combi-test 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1927 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-07-17 09:37:51 +00:00
wetzel
bf4ff8c853 added test jig, fixed some bugs and inverted the processing order 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1909 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-07-10 12:29:58 +00:00
stephan
9463bdfa4c add two lib modules 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1908 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-07-10 11:14:21 +00:00
stephan
045d1e1057 test for wa==ra in SIMULATION 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1890 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-07-07 22:38:52 +00:00
stephan
2fc99211c0 add CLKINT drivers to high fanout filter clks, fix sram defines 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1867 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-07-04 11:40:09 +00:00
stephan
488c7809d3 add SEU to L3 code RAM 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1856 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-07-03 15:55:00 +00:00
stephan
999a90dbac add afull to bfifo, used for serfifo 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1701 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-05-24 06:51:34 +00:00
stephan
3739232dab replace spififo with EDAC bfifo(16-bit) in secondcyclone slave 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1688 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-05-21 21:23:36 +00:00
stephan
ce172e6a1e Really fix heteptana ARx vs ATX confusion 
Fix GENSRAMs in sfilter for ACTEL pickyness


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1649 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-05-08 11:28:16 +00:00
wetzel
d3d6a1e155 Corrected some typing mistakes 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1491 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-02-05 15:20:35 +00:00
stephan
6e7c9d9ca2 make flyrena compuile in Quartus, adapt flyrena to heteptdig 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1484 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-01-31 14:30:18 +00:00
stephan
56a507510a 36 bit Actel RAMs 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1483 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-01-31 12:46:59 +00:00
wetzel
647f57ff97 Added 36 Bit memories 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1481 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-01-31 12:20:12 +00:00
stephan
578ba6b681 integrate Actel RAMS into the backend 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1480 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-01-31 11:44:13 +00:00
wetzel
ba17d09062 Actel memory modules and simulation modules are working so far. Tested by simulation 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1479 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-01-30 13:21:48 +00:00
wetzel
6a91733a8b Further developement of memory modules, partly redesign. Not finished until now! 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1478 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-01-29 15:41:37 +00:00
wetzel
990be492d9 Replaced memory wasting module from Actel by a wrapper. 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1472 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-01-25 11:52:20 +00:00
wetzel
3608174856 Corrected an error 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1470 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-01-25 09:16:39 +00:00
stephan
3f59e3ced6 move countbits.v to library 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1448 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-01-09 13:42:40 +00:00
stephan
a9953050eb backend in flyrena fits inside cyclon 3c25 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1432 bc5caf13-1734-44f8-af43-603852e9ee25
 2013-01-03 00:44:07 +00:00