Stephan/solo_altera
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5 commits

Author SHA1 Message Date
stephan
34c3a1c86e dorn/altera: bitfile for pulser test on 2020-04-16 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@8054 bc5caf13-1734-44f8-af43-603852e9ee25
 2020-04-17 15:30:32 +00:00
stephan
2018194748 darena: 
add scangen
	scope.extrig(trigger)
	fix endianess of pha (LE, same as clock)
	delay sa_init, to allow for 8 det readout at 16MHz


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@8025 bc5caf13-1734-44f8-af43-603852e9ee25
 2020-03-31 23:47:58 +00:00
stephan
82bef8d259 dorn: 
split darena.v from dorn.v
	rule to collect all Verilog sources in vsrc
	define WITH_* in Makefile and qsf


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@8012 bc5caf13-1734-44f8-af43-603852e9ee25
 2020-03-20 03:01:34 +00:00
stephan
f79f67b153 darena bitfile 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7987 bc5caf13-1734-44f8-af43-603852e9ee25
 2020-03-13 11:35:30 +00:00
stephan
711f7f90e4 darena: scope sim, target Altera 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7983 bc5caf13-1734-44f8-af43-603852e9ee25
 2020-03-12 23:59:28 +00:00