Stephan/solo_altera
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Author SHA1 Message Date
stephan
04ddd1fa55 heteptdig em/v06: new synthesis, with an inferred RAM that is not SEU safe 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3607 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-11 13:43:33 +00:00
terasa
58d0228308 ixrc.py: Adapted temperature readout code. 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3606 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-11 11:37:00 +00:00
stephan
76efe1d429 heteptdif em/v06: update sdc file 
clock uncerteainty to model Xtal duty cycle ??
 	more or less complete IO contraints
	clock phases


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3605 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-10 22:41:58 +00:00
stephan
a1c8c277b2 heteptdig em/v06: add syn_preserve to IO registers 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3604 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-10 22:39:53 +00:00
stephan
41d63828c2 heteptana: merge -c 3599,3602 from em/v04 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3603 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-10 20:09:43 +00:00
stephan
a41b1a2312 heteptana em/v04: 
add syn_preserve to input registers, so they will not be replicated for fanout
	fix declaration after use
	full constrain IO timing
	add clock uncertainty, will this cover dutycycle uncertainty?
	add NO_BCHANNEL netlist


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3602 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-10 16:08:30 +00:00
stephan
c58d90f8f5 heteptana em/v04 synthesis: again with Libero 9.2 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3601 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-09 16:14:31 +00:00
stephan
44f21417f7 heteptana em/vo4 synthesis with synopsys from libero 9.1 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3600 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-09 15:54:12 +00:00
stephan
f2e0003f78 heteptana em/v04: synthesis: delare reg before use 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3599 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-09 12:39:09 +00:00
stephan
bc3fbd847d heteptana em/v04: synthesis with libero 9.2 version of synopsis: G-2012.09A-SP4 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3598 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-09 12:25:46 +00:00
stephan
bebd2827ec heteptana em/v04: fix Makefile for sim of actel.v 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3597 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-09 11:51:28 +00:00
terasa
2e061129e4 pipe.py: Reverted changes by rasch, and copied changes to pipe_rasch.py. Please only check in tested and working code, which does not break previous functionality. 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3596 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-08 19:47:30 +00:00
stephan
ea7e1216fc heteptdig em/v06: merge -c 3548,3592-3593 
Use two words in pha.pha_acc_mem for wptr and tcnt.
	This allows to use the full 24 bits for tcnt in the PHA buffers.


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3595 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-08 08:19:52 +00:00
stephan
18a5f147c8 pha: remove obsolete TODO comment 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3594 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-08 08:16:37 +00:00
stephan
667bc29959 pha: 
Use only one RAM block for pha_acc_mem.
	The SUE of the removed RAM block causes different PRNG sequences 
	for the analog input data.
	Also: pass -v to vvp.


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3593 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-07 19:25:37 +00:00
stephan
bf99b86424 pha: 
Use separate memory in pha_acc_mem for tcnt and wptr.
	This allows for 24 bit tcnt without an extra RAM block.
	The extra RAM block is still there, not to mess up the PRNG.
	The next commit will have the extra RAM removed and a 
	new gold file.


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3592 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-07 15:47:13 +00:00
stephan
e0fb0e2176 heteptana: merge -c 3578 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3591 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-06 15:13:58 +00:00
stephan
ffc966c6c8 heteptana/em/v04: remove a reference to v03 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3590 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-05 13:58:40 +00:00
wetzel
9fc7249fd1 ... 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3589 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-05 12:57:43 +00:00
wetzel
fc11b6d5ef icu-message.txt: added assignment to conf bits for Step l1 config 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3588 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-05 12:57:29 +00:00
wetzel
c5bd9940e5 step: changed assignment of bits in l1/l2 config 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3587 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-05 12:56:38 +00:00
stephan
aff27ae183 heteptdig em/v06: merge various fixes and cleanups 
pha reset and enables
	initial statements (not supported for ACTEL target)
	comments


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3586 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-04 16:13:07 +00:00
stephan
8c7c6b2e81 heteptdig: add actel.v lib to Makefile 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3585 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-04 16:09:43 +00:00
stephan
036e4e0559 solomsg: MSG0 enables reassignment 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3584 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-04 16:08:45 +00:00
terasa
3f76ea93b5 ppss_table.py: Added some typechecks and exception handling. 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3583 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-04 14:58:47 +00:00
terasa
5c8eda23f0 ppss_table.py: Initial commit of python ppss_table creator. 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3582 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-04 14:49:00 +00:00
kruse
2f949071eb changed slew rates of non LVPECL signals connected to the IdeF-X from High to Low 
signals are: SC and STROBEn

git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3581 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-04 14:32:00 +00:00
wetzel
3bf27459c2 itf_parser.c: Added tabstop for Moritz. 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3580 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-04 14:15:05 +00:00
stephan
10e8e5dac5 heteptdig em/v06: copy actel.v again 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3579 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-04 11:01:50 +00:00
stephan
583df692db heteptana em/v04: remove iopad models from toplevel file, use library instead 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3578 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-04 10:57:51 +00:00
stephan
13d8d2f942 actel.v: move one directory down 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3577 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-04 10:57:12 +00:00
stephan
3c32880b12 heteptana em/v04: copy actel.v 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3576 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-04 10:52:41 +00:00
terasa
f308a7679a steinrc.py: Changed read_delay calculation to use ceil instead of normal rounding. Use TEMP sensor on DIGITAL board. 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3575 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-03 11:22:10 +00:00
terasa
994da61de7 itf_parser.c: removed whitespace in formatting. 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3574 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-03 11:20:36 +00:00
wetzel
1f03317a7e step low speed stream: added gab between last put and submit 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3573 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-02 13:01:05 +00:00
wetzel
432db47693 actel sim models: created file for actel specific sim models 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3572 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-02 12:15:01 +00:00
wetzel
b04721fc76 step/Makefile: moved CLK- and LVPECL-Buffer to actel.v 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3571 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-02 12:14:20 +00:00
wetzel
374c5b0519 step: changed name of EEPROM_BUSY to EEPROM_nBUSY 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3570 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-12-02 11:31:14 +00:00
stephan
6bca43827f stein_ix: fix baseline bit in stream data 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3569 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-11-28 18:58:13 +00:00
stephan
61accc3423 rpigse: 
Add fifo header mask registers in the FPGA.
	Add python functions to configure FIFOs and routing.


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3568 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-11-28 18:45:59 +00:00
stephan
77032048b9 packetfifo: fix match validation timing 
for the mask match case, the validation is not normally required


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3567 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-11-28 18:44:39 +00:00
panitzsch
9423483f02 ixrc.py: Removed read code in setters. Default values for threshholds is 63 for thresholds and 0 for everything else. 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3566 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-11-28 15:12:57 +00:00
terasa
595a2f8a34 itf_parser.c: step_event: data should be integer, and updated description. 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3565 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-11-28 14:09:17 +00:00
terasa
1a56092a4a itf_parser.c: Added hexdump function, reworked STEP parser. 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3564 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-11-28 13:13:23 +00:00
stephan
c3f5e2ff54 rpigse: add routing() and packetfifo_config() 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3563 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-11-28 11:14:29 +00:00
wetzel
3dbb0a6e2e step: reverted some changes and fixed wrong namings 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3562 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-11-28 10:11:17 +00:00
stephan
108ff316a4 stein: fix ttf_len 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3561 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-11-28 09:30:00 +00:00
stephan
9c641365d8 stein: lss and hss fixes 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3560 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-11-27 23:59:22 +00:00
stephan
70b9cc32d7 heteptdig: gold with initials 
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3559 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-11-27 22:58:34 +00:00
stephan
a1989161df backend+: 
Review power on reset. 
	Add initial statements for synthesis, in case the
	target supports a define power on state. 


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3558 bc5caf13-1734-44f8-af43-603852e9ee25
 2014-11-27 20:50:02 +00:00