Commit graph

9,307 commits

Author SHA1 Message Date
stephan
4fbbf5d0f7 fix bottom copper around detector hole
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1548 bc5caf13-1734-44f8-af43-603852e9ee25
2013-03-06 10:39:30 +00:00
stephan
bcd1ac0cc5 fix silk outline of detector chip
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1547 bc5caf13-1734-44f8-af43-603852e9ee25
2013-03-06 10:35:49 +00:00
stephan
ca408f4ab9 add Makefile
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1546 bc5caf13-1734-44f8-af43-603852e9ee25
2013-03-06 10:21:06 +00:00
stephan
187c8c4b3a The metal areas for glueing the ASIC and detector were enlarged
pretty much as requested.


From: Craig S Tindall <cstindall@lbl.gov>
Subject: Re: STEIN detector bonding / hybrid board
To: Stephan Boettcher <boettcher@physik.uni-kiel.de>
CC: Wimmer-Schweingruber <wimmer@physik.uni-kiel.de>,
        Lars Seimetz <seimetz@physik.uni-kiel.de>,
        "Chr. Terasa" <terasa@physik.uni-kiel.de>,
        Cesar Martin <martin@physik.uni-kiel.de>,
        GEVIN Olivier <olivier.gevin@cea.fr>,
        Limousin Olivier <olivier.limousin@cea.fr>,
        HUYNH Duc-Dat <duc-dat.huynh@cea.fr>,
        Lauri Panitzsch <panitzsch@physik.uni-kiel.de>
Date: Thu, 28 Feb 2013 11:20:09 -0800

With regard to the size of the board opening, I printed out a scale
model of the board to see how it will look and see what the tolerance
is around the edges.  Normally I mount the detector by holding with
teflon tweezers on the edges.  The tolerances here are quite tight for
this method, so I may have to try using a vacuum pen.  The traces are
very close also and I'm a little concerned that the epoxy might flow
out and short them.  If it's possible, I would like to request that we
make an opening and metal like the one shown in the drawing that I've
attached.  The two tabs will give quite a bit more area to hold the
detector, and I've increased the size of the detector die by 500um in
all directions.  The tan area is the metal on the board.  The
dimensions are in microns.

It looks as if four of the small pixels are not being used and are
just grounded to one of the traces.  Is this correct?  Since the
photomasks have not been fabricated yet, I can simply eliminate these
if they are not used.  Then they won't need to be wirebonded.  Perhaps
I could even extend the die another 500um in three directions to make
the placing and gluing task easier.  Is there any reason other than
minimizing the wirebond length that the overlap between the detector
and the board needs to be so small?

I also checked the wirebonding of the ASIC.  I'm not sure about the
precise dimensions of the ASIC.  I measured roughly 6.56mm x 2.93mm on
an IDEF-BD chip.  This appears to leave about 300um of metal all
around the chip.  I'm trying to get in touch with the person who does
the wirebonding.  I'm not sure that the wirebonding tool is small
enough to allow us to make wirebonds to the metal that extends out
from underneath the chip.  That appears to be what is shown in the
"IDEF-X" drawing.  Is that correct?

Thanks,
Craig



git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1545 bc5caf13-1734-44f8-af43-603852e9ee25
2013-03-06 10:19:55 +00:00
stephan
fb97da65d5 From: Craig S Tindall <cstindall@lbl.gov>
Subject: Re: STEIN detector bonding / hybrid board
To: Stephan Boettcher <boettcher@physik.uni-kiel.de>
Date: Thu, 28 Feb 2013 11:20:09 -0800

Hello Stephan,

With regard to the size of the board opening, I printed out a scale
model of the board to see how it will look and see what the tolerance
is around the edges.  Normally I mount the detector by holding with
teflon tweezers on the edges.  The tolerances here are quite tight for
this method, so I may have to try using a vacuum pen.  The traces are
very close also and I'm a little concerned that the epoxy might flow
out and short them.  If it's possible, I would like to request that we
make an opening and metal like the one shown in the drawing that I've
attached.  The two tabs will give quite a bit more area to hold the
detector, and I've increased the size of the detector die by 500um in
all directions.  The tan area is the metal on the board.  The
dimensions are in microns.


FIRST STEP: T-shaped detector hole, detector dimensions as requested.
TODO: outer copper dimension of the (biased) detector gluing area.



git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1544 bc5caf13-1734-44f8-af43-603852e9ee25
2013-03-05 16:00:13 +00:00
stephan
7a1d242f5b From: Lars Seimetz <seimetz@physik.uni-kiel.de>
Subject: Re: vias in ept-flex-carriers zum venting ?
To: Stephan Böttcher <boettcher@physik.uni-kiel.de>
Date: Tue, 26 Feb 2013 08:56:19 +0100

Noch eins:

Habe gerade gemerkt, dass mit einem Si-Durchmesser "Flat-Flat" von
14,52 (+0/-0,050) und einem Cutout von 13 (+0/-X (X ==> Was hast du da
"gespect"?) ) ein nomineller Klebespalt von

14,52mm - 13mm = 1,52mm/2 = 0,76 mm entsteht.

Abzüglich Toleranzen sind das dann:

(14,52mm - 0,05mm) - (13mm - X) = 1,47mm /2 - X/2 = 0,74 - X/2

Das ist kleiner als die absolut minimalen 80um Kleberand, die Canberra
uns vorgegeben hat.

Vorschlag: Der Cutout "Flat-Flat" sollte mit 12,8 +0/-0,1 bemaßt
werden. Dann kann die Canberra-Fertigungstoleranz bleiben, Brockstedt
bekommt sein Zehntel Millimeter Toleranz und der Klebespalt bleibt in
jedem Fall zwischen 80 um und 90 um.

Gruß, Lars


outline centerline redrawn at 12.8mm flat-to-flat (was 12.9mm).  
Specification in the README updated.




git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1543 bc5caf13-1734-44f8-af43-603852e9ee25
2013-03-05 10:16:30 +00:00
stephan
b5f8e864e6 From: Lars Seimetz <seimetz@physik.uni-kiel.de>
Subject: Re: EPT interconnect detector package assembly scheme
To: Stephan Boettcher <boettcher@physik.uni-kiel.de>
Date: Thu, 28 Feb 2013 11:52:02 +0100

Nur nochmal zur Sicherheit:
Ich, bzw. CANBERRA, sieht z.Zt. ein elektrisch leitfähiges "Gummi" als
Ausgleichring unter dem "electron" detector vor. Das bedeuted nach
meinem Verständnis, dass alle Strukturen (sofern dort welche sind) auf
der Rückseite des Pi-Carriers auf Gehäuse und damit Instrument-Gorund
liegen. ==> Vias auf der Rückseite im Bereich dieses Gummirings ==>
Kurzschluss.

Wenn die Rückseite leer ist, also nur PI ohne vias, o.ä. ist alles ok.

Kannst' das mal bitte prüfen?


GND and signal vias were swapped in y-position.




git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1542 bc5caf13-1734-44f8-af43-603852e9ee25
2013-03-05 09:52:51 +00:00
stephan
b653035e79 fix png rule dependencies
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1541 bc5caf13-1734-44f8-af43-603852e9ee25
2013-03-05 09:41:08 +00:00
wetzel
2c623a7166 Fixed a bug of the point reading e_class
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1540 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-25 12:28:45 +00:00
wetzel
aea02f9cc9 Added a testbench and fixed some bugs
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1539 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-25 11:09:40 +00:00
stephan
f95950982b add rigid tolearances to README
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1538 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-25 09:30:42 +00:00
stephan
92856035e8 fix inner radius in one corner
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1537 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-25 09:30:29 +00:00
stephan
9a9122373b add rigid tolearances to READMEs
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1536 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-25 09:29:55 +00:00
stephan
7e24f9ac89 L3 review comments
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1535 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-22 21:26:33 +00:00
stephan
6cfc89d83c cpu module ports as needed by the backend
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1534 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-22 21:26:19 +00:00
stephan
cf2bcef40f new multiplier implementation
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1533 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-22 21:25:03 +00:00
stephan
a6b64d7748 new multiplier implementation
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1532 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-22 21:24:52 +00:00
stephan
85d2e78dd6 compression textbench runs successfully
encode design change:
 When L=0 and a nnorm number is send, do not update L.
 This is an optimization for very low bitrates.


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1531 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-22 00:47:57 +00:00
stephan
407d3da8cc finish compression implementation
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1530 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-21 00:59:07 +00:00
stephan
d792eb556c do not use separate testbench file
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1529 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-21 00:58:40 +00:00
stephan
f045ae2492 encode:
non-pipelined
  left aligned output
  testbench moved into source


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1528 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-21 00:57:58 +00:00
stephan
53be1082a7 fix connector pads for swapped flex layers
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1527 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-20 16:14:02 +00:00
stephan
ab03de01f2 Swap eptcarrier flex top and bottom side
to match the pinout of the Omentics-25pin connector on
the eptpreamps board.


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1526 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-20 15:20:32 +00:00
wetzel
303a2b4f87 ...
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1525 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-20 14:52:16 +00:00
stephan
a8afe367da ...
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1524 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-20 14:24:05 +00:00
stephan
8b3ce5c153 add comment for sim hack
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1523 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-20 13:09:16 +00:00
wetzel
0df2b3b68f Added adc.v, containing the adc controller for stein
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1522 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-20 13:01:02 +00:00
stephan
56192d4419 add gerber export rules
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1521 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-20 12:08:01 +00:00
stephan
a505a16f11 v01
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1520 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-20 12:05:01 +00:00
stephan
faff616f04 add channel Ids to silk
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1519 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-20 11:48:22 +00:00
stephan
dfb74a85f3 fix README for _nv doc layers
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1518 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-20 11:13:44 +00:00
stephan
d245218183 rename CONN2
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1517 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-20 11:02:34 +00:00
stephan
7604379960 add Id on pcb silk layer, README fixes
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1516 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-20 10:59:14 +00:00
stephan
521ee55147 adjust flex length to 30mm/30mm, misc
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1515 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-19 17:37:06 +00:00
stephan
8d988ab0dd revert changes to heteptana from the previous commit
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1514 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-18 20:01:52 +00:00
stephan
f3809c0269 avoid routing under Omnetics
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1513 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-18 19:56:12 +00:00
stephan
85c81bd01e accomodate split ept carrier design at the omnetics connector
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1512 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-18 19:16:04 +00:00
stephan
ada77f162b move findirena after def HK
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1511 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-15 15:15:18 +00:00
stephan
be4dde650a remove i128 serial number
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1510 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-15 15:11:22 +00:00
stephan
da963618c0 2.2us shaping and final thresholds
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1509 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-15 15:10:55 +00:00
stephan
7794938198 verbose findirena
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1508 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-15 15:10:25 +00:00
stephan
7dd7adb95c add scripts
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1507 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-15 15:03:16 +00:00
stephan
2ec71ffd1d add Makefile
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1506 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-15 14:55:46 +00:00
stephan
f41f4d8b32 FRED2 channel names
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1505 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-12 18:05:41 +00:00
stephan
9415619b91 move actel pinout to altera/actel
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1504 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-12 11:10:07 +00:00
wetzel
00047aefbb Added pinout file for HET/EPT analogue board
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1503 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-11 14:30:30 +00:00
stephan
d499c0442d The HET carrier thuinkness needs to be ≥1mm, because the A-detector
sensor housing cannot accomodate thinner carriers than 0.8mm.


git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1502 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-08 15:13:16 +00:00
stephan
af9df88ac6 add segments to Silicon
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1501 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-07 20:05:00 +00:00
stephan
52d171f0bf add hetbcarrier
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1500 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-07 19:50:40 +00:00
stephan
352cd87122 heta carrier v00
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@1499 bc5caf13-1734-44f8-af43-603852e9ee25
2013-02-07 14:30:23 +00:00