6b16b9c727
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@9190 bc5caf13-1734-44f8-af43-603852e9ee25
42 lines
1.1 KiB
Makefile
42 lines
1.1 KiB
Makefile
export PATH:=$(PATH):.
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VERILOG=iverilog
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VERILOGFLAGS = -v -DSIMULATION $($*_FLAGS)
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%.vvp:
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$(VERILOG) $(VERILOGFLAGS) -o $@ $^
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vcd/%.fst: %.vvp
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$< -fst | tee $*.log
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spi_slave.vvp: spi_slave.v spi_slave_test.v spi_master_adc.v spififo_sim.v conf_reg.v
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spififo.vvp: spififo_sim.v spififo_sim_test.v
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trigger.vvp: trigger.v trigger_test.v spi_slave.v spififo_sim.v conf_reg.v log2.v
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conf_reg.vvp: conf_reg.v conf_reg_test.v
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serializer_FLAGS = -s serializer_test -DSERIALIZER_TEST
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serializer_nopll_FLAGS = $(serializer_FLAGS) -DNO_PLLS
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serializer.vvp: serializer.v
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serializer_nopll.vvp: serializer.v
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SpW.vvp: SpW.v serializer.v
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SpW_FLAGS = -DSpW_TEST -sSpW1_test
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SpW3.vvp: SpW.v serializer.v
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SpW3_FLAGS = -DSpW_TEST -sSpW3_test
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lasc.vvp: lasc.v conf_reg.v mega/fifo16.v
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lasc_FLAGS = -s lasc_test -DLASC_TEST
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utick.vvp: utick.v
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utick_FLAGS = -s utick_test -DUTICK_TEST
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pll192.vvp: pll192_sim.v pll192_test.v
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pll192_FLAGS = -s pll192_test -DPLL192_TEST
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slow_clock.vvp: slow_clock.v
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slow_clock_FLAGS = -s sclk_to_fclk_test -DSCLK_TO_FCLK_TEST
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i2c.vvp: i2c.v
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i2c_FLAGS = -s i2c_test -DI2C_TEST
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i2cm.vvp: i2c.v spififo_sim.v
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i2cm_FLAGS = -s i2cm_test -DI2CM_TEST
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