git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@9212 bc5caf13-1734-44f8-af43-603852e9ee25
60 lines
1.9 KiB
Makefile
60 lines
1.9 KiB
Makefile
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V=v1
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#VERILOG=/usr/local/bin/iverilog
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VERILOG=/usr/bin/iverilog
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VERILOGFLAGS = -v -Wall -Wno-timescale -DSIMULATION $($*_FLAGS)
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%.vvp:
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-grep TODO $(filter %.v,$^) > TODO.$*
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$(VERILOG) $(VERILOGFLAGS) -o $@ $(filter %.v,$^)
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vcd/%.lxt: %.vvp
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$< -lxt2 | tee $*.log
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.PRECIOUS: vcd/%.lxt
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VPATH=../../altera:../../altera/mega:../../hetept/altera:\
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../../irena/altera/adc128:../../irena/altera/direna:\
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../../sirena/altera:../../nm64/altera
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rpirena_FLAGS = -srpirena_test -DIRENACORE -DRPIRENA_TEST -DNOHALFCLK -DWITH_SPI_SSEL \
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-DHAVE_ABT2F -DINFERRED_SRAM -DTWOTHR -DI2CM
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rpirena.vvp: rpirena.v i2c.v \
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frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v \
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frontend_test.v fifo8_sim.v hkadc.v adc128s102.v pulser.v \
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filter.v sfilter.v irena_core.v adccntl.v itof.v \
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direna_test.v serializer.v countbits.v mem.v nmcounter.v
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ifeq ($V,10)
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QUARTUS=/usr/local/quartus/intelFPGA_lite/20.1/quartus
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else
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QUARTUS=/usr/local/quartus/altera13.1/quartus
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#QUARTUS=/usr/local/quartus/altera9.1sp1/quartus
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endif
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export PATH:=$(PATH):$(QUARTUS)/bin
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QDIR=quartus
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$(QDIR)/%.rbf: %.qpf %.qsf %.sdc
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quartus_map $<
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quartus_fit $<
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quartus_asm $<
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quartus_sta $<
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grep -i warning $(QDIR)/$*.*.rpt > $*.warnings
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FRONTEND = conf_reg.v spi_slave.v pll384.v spififo.v frontend.v packetfifo.v
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HKADC = hkadc.v adc128s102.v
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IRENA = filter.v sfilter.v irena_core.v adccntl.v itof.v
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GSE48 = sologse48.v icucore.v uart.v memory.v secondcyclone.v serializer.v
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$(QDIR)/rpirena.rbf: rpirena.v $(FRONTEND) $(HKADC) $(IRENA) i2c.v
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$(QDIR)/rpirena10.rbf: rpirena.v $(FRONTEND) $(HKADC) $(IRENA)
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rpigse_FLAGS = -srpigse_test -DRPIGSE_TEST \
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-DSOLOGSE48 -DWITH_SPI_SSEL -DSER_FIFO_ALTERA
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rpigse.vvp: rpirena.v sologse48.v \
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frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v countbits.v \
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frontend_test.v fifo8_sim.v hkadc.v adc128s102.v \
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icucore.v uart.v memory.v secondcyclone.v serializer.v
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$(QDIR)/rpigse.rbf: rpirena.v $(FRONTEND) $(HKADC) $(GSE48)
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