c488a1cfee
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@3840 bc5caf13-1734-44f8-af43-603852e9ee25
135 lines
15 KiB
Text
135 lines
15 KiB
Text
rpigse.asm.rpt:Info: Quartus II Assembler was successful. 0 errors, 0 warnings
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rpigse.fit.rpt: 5. I/O Assignment Warnings
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rpigse.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
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rpigse.fit.rpt:; I/O Assignment Warnings ;
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rpigse.fit.rpt:Warning: PLL "pll384:pll0|altpll:altpll_component|altpll_c433:auto_generated|pll1" has parameter clk1_counter set to C1 specified but port CLK[1] is not connected
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rpigse.fit.rpt:Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.
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rpigse.fit.rpt:Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
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rpigse.fit.rpt:Warning: Following 4 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
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rpigse.fit.rpt: Warning: Pin "LRTx[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRTx[2](n)"
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rpigse.fit.rpt: Warning: Pin "LRTx[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRTx[1](n)"
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rpigse.fit.rpt: Warning: Pin "LRx[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRx[2](n)"
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rpigse.fit.rpt: Warning: Pin "LRx[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LRx[1](n)"
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rpigse.fit.rpt:Warning: Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
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rpigse.fit.rpt:Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
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rpigse.fit.rpt:Warning: 41 pins must meet Altera requirements for 3.3, 3.0, and 2.5-V interfaces. Refer to the device Application Note 447 (Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems).
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rpigse.fit.rpt:Warning: PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447.
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rpigse.fit.rpt:Warning: Following 33 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
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rpigse.fit.rpt:Info: Quartus II Fitter was successful. 0 errors, 13 warnings
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rpigse.map.rpt:; CSn ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpigse.map.rpt:; SCLKn ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpigse.map.rpt:; dout1 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpigse.map.rpt:; dine ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpigse.map.rpt:; n ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpigse.map.rpt:; Tx_busy ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpigse.map.rpt:; Tx_full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpigse.map.rpt:; Rx_busy ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpigse.map.rpt:; Rx_brk ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpigse.map.rpt:; Rx_attn ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpigse.map.rpt:; rbi ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (1 bits) it drives. The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
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rpigse.map.rpt:; halffull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpigse.map.rpt:; attn ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpigse.map.rpt:; c1 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpigse.map.rpt:; c4 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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rpigse.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../hetept/altera/hkadc.v(9)
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rpigse.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../hetept/altera/hkadc.v(30)
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rpigse.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(13)
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rpigse.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(15)
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rpigse.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(82)
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rpigse.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/serializer.v(188)
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rpigse.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(128): Parameter Declaration in module "pps_gen" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpigse.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(129): Parameter Declaration in module "pps_gen" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpigse.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(96): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpigse.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(97): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpigse.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(98): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpigse.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(99): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpigse.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(100): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at rpirena.v(144): truncated value with size 32 to match size of target (4)
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at rpirena.v(191): truncated value with size 32 to match size of target (27)
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(97): truncated value with size 32 to match size of target (4)
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(253): truncated value with size 32 to match size of target (8)
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(255): truncated value with size 32 to match size of target (8)
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(70): truncated value with size 32 to match size of target (3)
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(141): truncated value with size 32 to match size of target (10)
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(162): truncated value with size 32 to match size of target (10)
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(12): truncated value with size 32 to match size of target (10)
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at sologse48.v(62): truncated value with size 32 to match size of target (16)
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at icucore.v(138): truncated value with size 32 to match size of target (11)
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at icucore.v(149): truncated value with size 32 to match size of target (16)
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(90): truncated value with size 32 to match size of target (4)
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(348): truncated value with size 32 to match size of target (9)
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(361): truncated value with size 32 to match size of target (4)
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at hkadc.v(55): truncated value with size 32 to match size of target (3)
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at adc128s102.v(129): truncated value with size 32 to match size of target (4)
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rpigse.map.rpt:Warning (10230): Verilog HDL assignment warning at rpirena.v(213): truncated value with size 32 to match size of target (7)
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rpigse.map.rpt:Warning: 6 hierarchies have connectivity warnings - see the Connectivity Checks report folder
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rpigse.map.rpt:Warning: The following nodes have both tri-state and non-tri-state drivers
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rpigse.map.rpt: Warning: Inserted always-enabled tri-state buffer between "PP[0]" and its non-tri-state driver.
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rpigse.map.rpt: Warning: Inserted always-enabled tri-state buffer between "PP[1]" and its non-tri-state driver.
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rpigse.map.rpt: Warning: Inserted always-enabled tri-state buffer between "PP[2]" and its non-tri-state driver.
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rpigse.map.rpt: Warning: Inserted always-enabled tri-state buffer between "EE[0]" and its non-tri-state driver.
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rpigse.map.rpt: Warning: Inserted always-enabled tri-state buffer between "EE[1]" and its non-tri-state driver.
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rpigse.map.rpt: Warning: Inserted always-enabled tri-state buffer between "EE[2]" and its non-tri-state driver.
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rpigse.map.rpt: Warning: Inserted always-enabled tri-state buffer between "EE[3]" and its non-tri-state driver.
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rpigse.map.rpt: Warning: Inserted always-enabled tri-state buffer between "EE[4]" and its non-tri-state driver.
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rpigse.map.rpt: Warning: Inserted always-enabled tri-state buffer between "EE[5]" and its non-tri-state driver.
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rpigse.map.rpt:Warning: The following bidir pins have no drivers
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rpigse.map.rpt: Warning: Bidir "gpio17" has no driver
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rpigse.map.rpt: Warning: Bidir "gpio22" has no driver
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rpigse.map.rpt: Warning: Bidir "gpio27" has no driver
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rpigse.map.rpt: Warning: Bidir "gpclk0" has no driver
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rpigse.map.rpt: Warning: Bidir "SCL" has no driver
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rpigse.map.rpt: Warning: Bidir "SDA" has no driver
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rpigse.map.rpt: Warning: Bidir "PP[3]" has no driver
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rpigse.map.rpt: Warning: Bidir "PP[4]" has no driver
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rpigse.map.rpt: Warning: Bidir "PP[5]" has no driver
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rpigse.map.rpt: Warning: Bidir "DD[0]" has no driver
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rpigse.map.rpt: Warning: Bidir "DD[1]" has no driver
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rpigse.map.rpt: Warning: Bidir "DD[2]" has no driver
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rpigse.map.rpt: Warning: Bidir "DD[3]" has no driver
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rpigse.map.rpt: Warning: Bidir "DD[4]" has no driver
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rpigse.map.rpt: Warning: Bidir "EE[6]" has no driver
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rpigse.map.rpt: Warning: Bidir "EE[7]" has no driver
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rpigse.map.rpt: Warning: Bidir "EE[8]" has no driver
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rpigse.map.rpt: Warning: Bidir "EE[9]" has no driver
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rpigse.map.rpt: Warning: Bidir "EE[10]" has no driver
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rpigse.map.rpt: Warning: Bidir "LL[0]" has no driver
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rpigse.map.rpt: Warning: Bidir "LL[1]" has no driver
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rpigse.map.rpt: Warning: Bidir "LL[2]" has no driver
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rpigse.map.rpt: Warning: Bidir "LL[3]" has no driver
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rpigse.map.rpt: Warning: Bidir "LL[4]" has no driver
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rpigse.map.rpt:Warning: TRI or OPNDRN buffers permanently enabled
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rpigse.map.rpt: Warning: Node "PP[0]~synth"
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rpigse.map.rpt: Warning: Node "PP[1]~synth"
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rpigse.map.rpt: Warning: Node "PP[2]~synth"
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rpigse.map.rpt: Warning: Node "EE[0]~synth"
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rpigse.map.rpt: Warning: Node "EE[1]~synth"
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rpigse.map.rpt: Warning: Node "EE[2]~synth"
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rpigse.map.rpt: Warning: Node "EE[3]~synth"
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rpigse.map.rpt: Warning: Node "EE[4]~synth"
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rpigse.map.rpt: Warning: Node "EE[5]~synth"
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rpigse.map.rpt:Warning: Output pins are stuck at VCC or GND
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rpigse.map.rpt: Warning (13410): Pin "SCLK[4]" is stuck at GND
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rpigse.map.rpt: Warning (13410): Pin "SCLK[3]" is stuck at GND
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rpigse.map.rpt: Warning (13410): Pin "SCLK[2]" is stuck at GND
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rpigse.map.rpt: Warning (13410): Pin "SCLK[1]" is stuck at GND
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rpigse.map.rpt: Warning (13410): Pin "nCS[4]" is stuck at VCC
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rpigse.map.rpt: Warning (13410): Pin "nCS[3]" is stuck at VCC
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rpigse.map.rpt: Warning (13410): Pin "nCS[2]" is stuck at VCC
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rpigse.map.rpt: Warning (13410): Pin "nCS[1]" is stuck at VCC
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rpigse.map.rpt:Warning: PLL "pll384:pll0|altpll:altpll_component|altpll_c433:auto_generated|pll1" has parameter clk1_counter set to C1 specified but port CLK[1] is not connected
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rpigse.map.rpt:Warning: PLL "pll384:pll0|altpll:altpll_component|altpll_c433:auto_generated|pll1" has parameter clk1_counter set to C1 specified but port CLK[1] is not connected
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rpigse.map.rpt:Warning: Design contains 10 input pin(s) that do not drive logic
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rpigse.map.rpt: Warning (15610): No output dependent on input pin "spi_cs[1]"
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rpigse.map.rpt: Warning (15610): No output dependent on input pin "LRTx[2]"
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rpigse.map.rpt: Warning (15610): No output dependent on input pin "LRTx[1]"
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rpigse.map.rpt: Warning (15610): No output dependent on input pin "SDATA[4]"
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rpigse.map.rpt: Warning (15610): No output dependent on input pin "SDATA[3]"
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rpigse.map.rpt: Warning (15610): No output dependent on input pin "SDATA[2]"
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rpigse.map.rpt: Warning (15610): No output dependent on input pin "SDATA[1]"
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rpigse.map.rpt: Warning (15610): No output dependent on input pin "CC[0]"
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rpigse.map.rpt: Warning (15610): No output dependent on input pin "CC[1]"
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rpigse.map.rpt: Warning (15610): No output dependent on input pin "CC[2]"
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rpigse.map.rpt:Info: Quartus II Analysis & Synthesis was successful. 0 errors, 100 warnings
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rpigse.sta.rpt:Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings
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