0f8e1fb9eb
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5480 bc5caf13-1734-44f8-af43-603852e9ee25
102 lines
3.5 KiB
Makefile
102 lines
3.5 KiB
Makefile
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VERILOG=/usr/local/bin/iverilog
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VVP=$(subst iverilog,vvp,$(VERILOG))
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#VERILOG=/usr/bin/iverilog
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VERILOGFLAGS = -v -Wall -Wno-timescale -DSIMULATION $($*_FLAGS)
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%.vvp: %.v
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grep TODO $(filter %.v,$^) > TODO.$*
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$(VERILOG) $(VERILOGFLAGS) -o $@ $(filter %.v,$^)
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vcd/%.lxt: %.vvp
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$(VVP) -v $< -lxt2 | tee $*.log
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.PRECIOUS: vcd/%.lxt
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VPATH=../../arena/altera:../../areana/altera/adc128:\
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../../irena/altera/adc128:../../hetept/altera:\
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../../sirena/altera:../../sirena/altera/l3:../../sirena/altera/encode:\
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../../altera:../../altera/mega:../../altera/actel
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flyrena_RAM = -DINFERRED_SRAM
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flyrena_FLAGS = -DFLYRENA_TEST -DHETEPTANA_TEST -DUART3MHZ -DGENSRAM $(flyrena_RAM) -s flyrena_test
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flyrena.vvp: flyrena.v secondcyclone.v serializer.v \
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countbits.v actel.v \
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frontend.v spi_slave.v spififo_sim.v conf_reg.v packetfifo.v \
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ad9649.v frontend_test.v fifo8_sim.v \
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adc_data.v oscilloscope.v spi_master_adc.v \
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icucore.v \
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heteptana.v sfilter.v adc128s102.v hkadc.v pulser.v \
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heteptcore.v backend.v opheater.v por.v \
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message.v uart.v crc.v \
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msg_regs.v ppsschedule.v l3code.v hamming.v \
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pulse.hex ppsschedule.hex memport.v eeprom.v \
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compression.v encode.v itof.v log2by8.v \
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processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v \
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adderi.v mult.v bitrange.v \
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mem.v l3registerfile.v counters.v fifo.v pha.v
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heteptdig_RAM = -DACTEL_SRAM -DSEU_RATE=50
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heteptdig_SRAM = -DMEM16EE
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heteptdig_OPTIONS =
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heteptdig_FLAGS = -s heteptdig_test $(heteptdig_OPTIONS) \
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-DHETEPTDIG_TEST -DHETEPTANA_TEST \
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-DARxSTREAM \
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-DUART3MHZ -DM24MHZ $(heteptdig_RAM) $(heteptdig_SRAM)
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ce4dig_RAM = -DACTEL_SRAM -DSEU_RATE=50
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ce4dig_SRAM = -DMEM16EE
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ce4dig_OPTIONS =
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ce4dig_FLAGS = -s ce4dig_test $(ce4dig_OPTIONS) \
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-DChangE4 -DREMOTE_ADC -DNO_MSG_TIMEOUT -DUART_PARITY=1 \
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-DCE4DIG_TEST -DHETEPTANA_TEST \
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-DARxSTREAM \
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-DUART3MHZ -DM24MHZ $(ce4dig_RAM) $(ce4dig_SRAM)
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HETEPTDIG_SOURCES = secondcyclone.v serializer.v \
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icucore.v \
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heteptana.v sfilter.v adc128s102.v hkadc.v pulser.v \
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heteptcore.v backend.v opheater.v por.v \
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message.v uart.v crc.v \
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msg_regs.v ppsschedule.v l3code.v hamming.v \
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pulse.hex ppsschedule.hex memport.v eeprom.v \
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compression.v encode.v itof.v log2by8.v \
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processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v \
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adderi.v mult.v bitrange.v \
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mem.v l3registerfile.v counters.v fifo.v pha.v \
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RAM64K36_sim.v memWxActel.v actel.v \
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mem36x128.v mem36x256.v mem36x512.v mem36x1024.v mem36x2048.v \
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mem72x128.v mem72x256.v mem72x512.v mem72x1024.v mem72x2048.v
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heteptdig.vvp: heteptdig.v $(HETEPTDIG_SOURCES)
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ce4dig.vvp: ce4dig.v $(HETEPTDIG_SOURCES)
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QUARTUS=/usr/local/quartus/altera9.1sp1/quartus
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export PATH:=$(PATH):$(QUARTUS)/bin
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%.rbf: %.qpf %.qsf %.sdc %.v \
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frontend.v spi_slave.v conf_reg.v packetfifo.v spififo.v
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quartus_map $<
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quartus_fit $<
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quartus_asm $<
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quartus_sta $<
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grep -i warning $*.*.rpt > $*.warnings
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FRONTEND = conf_reg.v spi_slave.v pll96.v spififo.v frontend.v packetfifo.v
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flyrena.rbf: spi_master_adc.v \
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$(FRONTEND) icucore.v \
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backend.v pha.v eeprom.v l3registerfile.v \
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arena.v adc_data.v oscilloscope.v \
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secondcyclone.v serializer.v pll240_96.v pll240d_96.v \
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message.v uart.v crc.v \
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msg_regs.v ppsschedule.v l3code.v hamming.v \
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pulse.hex ppsschedule.hex memport.v eeprom.v \
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compression.v encode.v itof.v \
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processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v \
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adderi.v mult.v bitrange.v \
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mem.v l3registerfile.v counters.v fifo.v pha.v
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ppsschedule.vvp: l3code.v hamming.v
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ppsschedule_FLAGS = -DPPSSCHEDULE_TEST -DINFERRED_SRAM -s ppsschedule_test
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