ea6fbc16cc
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@8444 bc5caf13-1734-44f8-af43-603852e9ee25
41 lines
1 KiB
Makefile
41 lines
1 KiB
Makefile
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PROJ=pirena
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VERILOG=/usr/local/bin/iverilog
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#VERILOG=/usr/bin/iverilog
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VERILOGFLAGS = -v -DSIMULATION $($*_FLAGS)
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%.vvp: %.v
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$(VERILOG) $(VERILOGFLAGS) -o $@ $^
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vcd/%.lxt: %.vvp
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$< -lxt2 | tee $*.log
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.PRECIOUS: vcd/%.lxt
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VPATH=.:./direna:../../altera:../../altera/mega:../../nm64/altera
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$(PROJ)_FLAGS = -D$(PROJ)_TEST -s $(PROJ)_test
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pirena.vvp: $(PROJ)_test.v frontend.v spi_slave.v spififo_sim.v \
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conf_reg.v packetfifo.v trigen.v countbits.v \
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ad7690.v frontend_test.v ltc2656.v
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QUARTUS=/usr/local/quartus/altera13.1/quartus
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export PATH:=$(PATH):$(QUARTUS)/bin
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MAPFLGS = $(patsubst %, --verilog_macro="%",$($*_MAPDEFS))
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QDIR=quartus
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$(QDIR)/%.rbf: %.qpf %.qsf %.sdc \
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frontend.v spi_slave.v conf_reg.v packetfifo.v spififo.v countbits.v
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quartus_map $< $(MAPFLGS)
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quartus_fit $<
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quartus_asm $<
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quartus_sta $<
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grep -i warning $(QDIR)/$*.*.rpt > $*.warnings
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ADC_SAMPLE_EARLY = ADC_SAMPLE_EARLY=1
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pirena_MAPDEFS = $(no_ADC_SAMPLE_EARLY)
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$(QDIR)/pirena.rbf: pirena.v ad7690.v trigen.v pll96.v ltc2656.v
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