cc538a2d02
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5729 bc5caf13-1734-44f8-af43-603852e9ee25
357 lines
51 KiB
Text
357 lines
51 KiB
Text
sirena_ce4.asm.rpt:Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
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sirena_ce4.fit.rpt: 5. I/O Assignment Warnings
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sirena_ce4.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
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sirena_ce4.fit.rpt:; I/O Assignment Warnings ;
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sirena_ce4.fit.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
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sirena_ce4.fit.rpt:Warning (15901): PLL "pll384:pll0|altpll:altpll_component|altpll_r273:auto_generated|pll1" has parameter clk0_counter set to C0 specified but port CLK[0] is not connected
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sirena_ce4.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
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sirena_ce4.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
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sirena_ce4.fit.rpt:Warning (176674): Following 7 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
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sirena_ce4.fit.rpt: Warning (176118): Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)"
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sirena_ce4.fit.rpt: Warning (176118): Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)"
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sirena_ce4.fit.rpt: Warning (176118): Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)"
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sirena_ce4.fit.rpt: Warning (176118): Pin "FE_clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "FE_clk(n)"
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sirena_ce4.fit.rpt: Warning (176118): Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
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sirena_ce4.fit.rpt: Warning (176118): Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
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sirena_ce4.fit.rpt: Warning (176118): Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
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sirena_ce4.fit.rpt:Warning (176251): Ignoring some wildcard destinations of fast I/O register assignments
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sirena_ce4.fit.rpt:Warning (169064): Following 16 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
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sirena_ce4.fit.rpt:Info: Quartus II 32-bit Fitter was successful. 0 errors, 14 warnings
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sirena_ce4.map.rpt:; afull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; empty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; empty3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; empty3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; empty3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; empty3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; empty3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; empty ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; empty3 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; ggo ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; q ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; error ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; single ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; error ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; single ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; pend ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; busy ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; d ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; mrb_l ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; usecond ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; utick ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; valid ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; idx ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; mask ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; a ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; rx_ack ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; d ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; q ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; afull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; rx_ferr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; halffull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; c1 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; c2 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:; c4 ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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sirena_ce4.map.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at pha.v(62)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(427)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(429)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(431)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(436)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(438)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(440)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(454)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(481)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(843)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(845)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(847)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(849)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(945)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(959)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(1085)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(1087)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(1089)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(1091)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(1193)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(1205)
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sirena_ce4.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at memport.v(1217)
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at uart.v(443): Parameter Declaration in module "uart" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at uart.v(473): Parameter Declaration in module "uart" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at uart.v(477): Parameter Declaration in module "uart" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at uart.v(478): Parameter Declaration in module "uart" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at uart.v(479): Parameter Declaration in module "uart" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at uart.v(480): Parameter Declaration in module "uart" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at message.v(153): Parameter Declaration in module "SpW_message" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at message.v(154): Parameter Declaration in module "SpW_message" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at message.v(155): Parameter Declaration in module "SpW_message" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at message.v(156): Parameter Declaration in module "SpW_message" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(123): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(171): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(173): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(174): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(175): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(176): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(191): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(498): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(516): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(534): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(564): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(622): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(623): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(639): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(640): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(641): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(642): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(644): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(645): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at backend.v(646): Parameter Declaration in module "backend" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(128): Parameter Declaration in module "pps_gen" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(129): Parameter Declaration in module "pps_gen" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(96): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(97): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(98): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(99): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at icucore.v(100): Parameter Declaration in module "icucore" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(449): Parameter Declaration in module "memasync32ee" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(450): Parameter Declaration in module "memasync32ee" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(451): Parameter Declaration in module "memasync32ee" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(659): Parameter Declaration in module "memasync16ee48" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(660): Parameter Declaration in module "memasync16ee48" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at memport.v(661): Parameter Declaration in module "memasync16ee48" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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sirena_ce4.map.rpt:Warning (10034): Output port "debug[4]" at sirena.v(26) has no driver
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sirena_ce4.map.rpt:Warning (10034): Output port "debug[6]" at sirena.v(26) has no driver
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(97): truncated value with size 32 to match size of target (4)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(253): truncated value with size 32 to match size of target (8)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(255): truncated value with size 32 to match size of target (8)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(70): truncated value with size 32 to match size of target (3)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(141): truncated value with size 32 to match size of target (10)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(162): truncated value with size 32 to match size of target (10)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (10)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at icucore.v(138): truncated value with size 32 to match size of target (10)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at icucore.v(149): truncated value with size 32 to match size of target (16)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(1328): truncated value with size 32 to match size of target (2)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at por.v(14): truncated value with size 32 to match size of target (8)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(63): truncated value with size 32 to match size of target (18)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(65): truncated value with size 32 to match size of target (18)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(504): truncated value with size 32 to match size of target (4)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at crc.v(65): truncated value with size 32 to match size of target (4)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at crc.v(18): truncated value with size 32 to match size of target (16)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at crc.v(22): truncated value with size 32 to match size of target (16)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at crc.v(27): truncated value with size 32 to match size of target (16)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(366): truncated value with size 32 to match size of target (4)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(383): truncated value with size 32 to match size of target (16)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(397): truncated value with size 32 to match size of target (13)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(238): truncated value with size 32 to match size of target (16)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(260): truncated value with size 32 to match size of target (27)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(262): truncated value with size 32 to match size of target (27)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(264): truncated value with size 32 to match size of target (27)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(389): truncated value with size 32 to match size of target (13)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(391): truncated value with size 32 to match size of target (13)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(396): truncated value with size 32 to match size of target (4)
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sirena_ce4.map.rpt:Warning (10030): Net "clkdiv[2..0]" at uart.v(381) has no driver or initial value, using a default initial value '0'
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at fifo.v(47): truncated value with size 32 to match size of target (8)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at fifo.v(61): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at fifo.v(63): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at fifo.v(98): truncated value with size 32 to match size of target (8)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at fifo.v(106): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(52): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(91): truncated value with size 32 to match size of target (4)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at uart.v(139): truncated value with size 32 to match size of target (1)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(158): truncated value with size 32 to match size of target (17)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(325): truncated value with size 32 to match size of target (4)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(326): truncated value with size 32 to match size of target (4)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(329): truncated value with size 32 to match size of target (4)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(334): truncated value with size 32 to match size of target (4)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(339): truncated value with size 32 to match size of target (4)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(342): truncated value with size 32 to match size of target (4)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(343): truncated value with size 32 to match size of target (4)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(440): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(441): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(442): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(443): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(444): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(445): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(446): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(447): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(448): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(449): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(450): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(451): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(452): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(453): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(454): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(455): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(465): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(466): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(468): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(471): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(473): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(476): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(478): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(483): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(486): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(488): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(491): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(493): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(495): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(496): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(497): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(498): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(503): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(546): truncated value with size 32 to match size of target (5)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(553): truncated value with size 32 to match size of target (16)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(558): truncated value with size 32 to match size of target (8)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(567): truncated value with size 66 to match size of target (64)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at evgen.v(42): truncated value with size 32 to match size of target (5)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at floats.v(32): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at floats.v(39): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at floats.v(273): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at floats.v(277): truncated value with size 32 to match size of target (18)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at floats.v(278): truncated value with size 32 to match size of target (18)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at floats.v(280): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at floats.v(158): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at floats.v(165): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at floats.v(174): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at floats.v(218): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at floats.v(225): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at floats.v(234): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at floats.v(235): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at floats.v(72): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at floats.v(79): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at counters.v(16): truncated value with size 32 to match size of target (16)
|
|
sirena_ce4.map.rpt:Warning (10036): Verilog HDL or VHDL warning at backend.v(216): object "t_count" assigned a value but never read
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at msg_regs.v(88): truncated value with size 32 to match size of target (16)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at msg_regs.v(95): truncated value with size 32 to match size of target (16)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at msg_regs.v(106): truncated value with size 32 to match size of target (16)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at msg_regs.v(117): truncated value with size 32 to match size of target (4)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at msg_regs.v(119): truncated value with size 32 to match size of target (4)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at l3code.v(186): truncated value with size 21 to match size of target (16)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at l3code.v(188): truncated value with size 21 to match size of target (16)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at l3code.v(190): truncated value with size 21 to match size of target (16)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at l3code.v(192): truncated value with size 21 to match size of target (16)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at l3code.v(227): truncated value with size 32 to match size of target (24)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at l3code.v(228): truncated value with size 32 to match size of target (16)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at counters.v(83): truncated value with size 32 to match size of target (7)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at counters.v(117): truncated value with size 32 to match size of target (30)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(21): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(24): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(27): truncated value with size 32 to match size of target (4)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(28): truncated value with size 32 to match size of target (27)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(39): truncated value with size 27 to match size of target (12)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(21): truncated value with size 32 to match size of target (7)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(24): truncated value with size 32 to match size of target (7)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(39): truncated value with size 27 to match size of target (3)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at ppsschedule.v(108): truncated value with size 32 to match size of target (12)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at ppsschedule.v(121): truncated value with size 32 to match size of target (3)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at ppsschedule.v(124): truncated value with size 32 to match size of target (3)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at ppsschedule.v(171): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at ppsschedule.v(183): truncated value with size 32 to match size of target (24)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at ppsschedule.v(220): truncated value with size 32 to match size of target (8)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(27): truncated value with size 32 to match size of target (4)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(47): truncated value with size 32 to match size of target (4)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(27): truncated value with size 32 to match size of target (3)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(47): truncated value with size 32 to match size of target (3)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(323): truncated value with size 32 to match size of target (19)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(324): truncated value with size 32 to match size of target (8)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(330): truncated value with size 32 to match size of target (8)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at memport.v(344): truncated value with size 32 to match size of target (26)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at eeprom.v(131): truncated value with size 32 to match size of target (2)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at eeprom.v(136): truncated value with size 32 to match size of target (7)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at eeprom.v(137): truncated value with size 32 to match size of target (8)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at eeprom.v(157): truncated value with size 32 to match size of target (14)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(72): truncated value with size 32 to match size of target (2)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(78): truncated value with size 32 to match size of target (5)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(96): truncated value with size 32 to match size of target (2)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(101): truncated value with size 32 to match size of target (5)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(207): truncated value with size 32 to match size of target (24)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(222): truncated value with size 32 to match size of target (5)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(248): truncated value with size 32 to match size of target (4)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(256): truncated value with size 32 to match size of target (9)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at pha.v(260): truncated value with size 32 to match size of target (9)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at l3registerfile.v(141): truncated value with size 32 to match size of target (8)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(46): truncated value with size 32 to match size of target (8)
|
|
sirena_ce4.map.rpt:Warning (10036): Verilog HDL or VHDL warning at processor.v(291): object "mux_jump" assigned a value but never read
|
|
sirena_ce4.map.rpt:Warning (10036): Verilog HDL or VHDL warning at processor.v(336): object "go_addi" assigned a value but never read
|
|
sirena_ce4.map.rpt:Warning (10036): Verilog HDL or VHDL warning at processor.v(336): object "go_add" assigned a value but never read
|
|
sirena_ce4.map.rpt:Warning (10036): Verilog HDL or VHDL warning at processor.v(336): object "go_sub" assigned a value but never read
|
|
sirena_ce4.map.rpt:Warning (10036): Verilog HDL or VHDL warning at processor.v(336): object "go_log" assigned a value but never read
|
|
sirena_ce4.map.rpt:Warning (10036): Verilog HDL or VHDL warning at processor.v(336): object "go_cmp" assigned a value but never read
|
|
sirena_ce4.map.rpt:Warning (10036): Verilog HDL or VHDL warning at processor.v(336): object "go_trim" assigned a value but never read
|
|
sirena_ce4.map.rpt:Warning (10036): Verilog HDL or VHDL warning at processor.v(336): object "go_brng" assigned a value but never read
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(547): truncated value with size 32 to match size of target (29)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(548): truncated value with size 32 to match size of target (29)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(557): truncated value with size 32 to match size of target (29)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(564): truncated value with size 32 to match size of target (29)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(572): truncated value with size 32 to match size of target (29)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(577): truncated value with size 32 to match size of target (29)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(585): truncated value with size 32 to match size of target (29)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(592): truncated value with size 32 to match size of target (29)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at processor.v(601): truncated value with size 29 to match size of target (1)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at adder.v(46): truncated value with size 32 to match size of target (28)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at adder.v(55): truncated value with size 32 to match size of target (28)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at adderi.v(23): truncated value with size 32 to match size of target (28)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at mult.v(27): truncated value with size 45 to match size of target (29)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at log7to4.v(33): truncated value with size 32 to match size of target (5)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at log7to4.v(36): truncated value with size 37 to match size of target (7)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at bitrange.v(15): truncated value with size 32 to match size of target (29)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at bitrange.v(16): truncated value with size 32 to match size of target (29)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at ppsschedule.v(325): truncated value with size 32 to match size of target (11)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at ppsschedule.v(326): truncated value with size 32 to match size of target (12)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at ppsschedule.v(439): truncated value with size 32 to match size of target (3)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at compression.v(171): truncated value with size 32 to match size of target (7)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at compression.v(186): truncated value with size 32 to match size of target (26)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at compression.v(196): truncated value with size 32 to match size of target (2)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at encode.v(34): truncated value with size 32 to match size of target (5)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at encode.v(84): truncated value with size 32 to match size of target (5)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at encode.v(86): truncated value with size 32 to match size of target (5)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at encode.v(91): truncated value with size 32 to match size of target (4)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at encode.v(93): truncated value with size 32 to match size of target (4)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at encode.v(116): truncated value with size 32 to match size of target (26)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at encode.v(117): truncated value with size 32 to match size of target (26)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(21): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(24): truncated value with size 32 to match size of target (6)
|
|
sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at itof.v(39): truncated value with size 24 to match size of target (12)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at log2by8.v(24): truncated value with size 32 to match size of target (5)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at log2by8.v(27): truncated value with size 32 to match size of target (5)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(641): truncated value with size 32 to match size of target (6)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(643): truncated value with size 32 to match size of target (6)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(655): truncated value with size 32 to match size of target (12)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at message.v(690): truncated value with size 32 to match size of target (12)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at opheater.v(37): truncated value with size 4 to match size of target (3)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at opheater.v(40): truncated value with size 16 to match size of target (13)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at opheater.v(52): truncated value with size 32 to match size of target (8)
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sirena_ce4.map.rpt:Warning (10230): Verilog HDL assignment warning at opheater.v(67): truncated value with size 32 to match size of target (24)
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sirena_ce4.map.rpt:Warning (12241): 21 hierarchies have connectivity warnings - see the Connectivity Checks report folder
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sirena_ce4.map.rpt:Warning (13039): The following bidir pins have no drivers
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sirena_ce4.map.rpt: Warning (13040): Bidir "FE_port[0]" has no driver
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sirena_ce4.map.rpt: Warning (13040): Bidir "FE_port[1]" has no driver
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sirena_ce4.map.rpt: Warning (13040): Bidir "FE_port[2]" has no driver
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sirena_ce4.map.rpt: Warning (13040): Bidir "FE_port[3]" has no driver
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sirena_ce4.map.rpt: Warning (13040): Bidir "FE_port[4]" has no driver
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sirena_ce4.map.rpt: Warning (13040): Bidir "FE_port[5]" has no driver
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sirena_ce4.map.rpt: Warning (13040): Bidir "FE_port[6]" has no driver
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sirena_ce4.map.rpt: Warning (13040): Bidir "FE_port[7]" has no driver
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sirena_ce4.map.rpt: Warning (13040): Bidir "FE_port[8]" has no driver
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sirena_ce4.map.rpt: Warning (13040): Bidir "FE_port[9]" has no driver
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sirena_ce4.map.rpt: Warning (13040): Bidir "FE_port[10]" has no driver
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sirena_ce4.map.rpt: Warning (13040): Bidir "FE_port[11]" has no driver
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sirena_ce4.map.rpt: Warning (13040): Bidir "FE_port[12]" has no driver
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sirena_ce4.map.rpt: Warning (13040): Bidir "FE_port[13]" has no driver
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sirena_ce4.map.rpt: Warning (13040): Bidir "FE_port[14]" has no driver
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sirena_ce4.map.rpt: Warning (13040): Bidir "FE_port[15]" has no driver
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sirena_ce4.map.rpt:Warning (13024): Output pins are stuck at VCC or GND
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sirena_ce4.map.rpt: Warning (13410): Pin "sram_ce[2]" is stuck at VCC
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sirena_ce4.map.rpt: Warning (13410): Pin "debug[6]" is stuck at GND
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sirena_ce4.map.rpt: Warning (13410): Pin "debug[4]" is stuck at GND
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sirena_ce4.map.rpt:Warning (15901): PLL "pll384:pll0|altpll:altpll_component|altpll_r273:auto_generated|pll1" has parameter clk0_counter set to C0 specified but port CLK[0] is not connected
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sirena_ce4.map.rpt:Warning (21074): Design contains 3 input pin(s) that do not drive logic
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sirena_ce4.map.rpt: Warning (15610): No output dependent on input pin "clk_T1"
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sirena_ce4.map.rpt: Warning (15610): No output dependent on input pin "trigger"
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sirena_ce4.map.rpt: Warning (15610): No output dependent on input pin "FE_clk"
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sirena_ce4.map.rpt:Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 297 warnings
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sirena_ce4.sta.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
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sirena_ce4.sta.rpt:Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning
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