f8fbbf3e9d
- add missing modules to qsf and Makefile - fixed settings for current version git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@5115 bc5caf13-1734-44f8-af43-603852e9ee25
151 lines
7.3 KiB
Makefile
151 lines
7.3 KiB
Makefile
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# need iverilog version 0.10 for signed integers
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# VERILOG=/usr/local/bin/iverilog
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VERILOG=iverilog
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VERILOGFLAGS = -v -Wall -Wno-timescale -DSIMULATION $(IVLFLAGS) $($*_FLAGS)
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%.vvp:
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$(VERILOG) $(VERILOGFLAGS) -o $@ $(filter %.v, $^)
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lxt/%.lxt: %.vvp
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mkdir -p lxt/
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$< -lxt2 | tee $*.log
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.PRECIOUS: lxt/%.lxt
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VPATH=../../irena/altera/adc128:../../altera:../../altera/mega:../../idef-x/altera:\
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../../altera/actel:../../sirena/altera:../../sirena/altera/l3:\
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../../sirena/altera/encode:../../hetept/altera:\
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../../arena/altera/idef-x:../../arena/altera
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stein.vvp: stein.v stein_core.v stein_pha.v frontend.v backend.v memport.v \
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message.v uart.v l3code.v crc.v msg_regs.v \
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mem.v fifo.v hamming.v counters.v \
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ppsschedule.v pha.v eeprom.v l3registerfile.v \
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processor.v l3regfifo.v adder.v adderi.v mult.v log7to4.v trim.v bitrange.v cmp.v \
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compression.v encode.v itof.v log2by8.v \
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opheater.v sfilter.v \
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stein_middleend.v stein_frontend.v clk_domain_switch.v stein_ix_controller.v stein_l1_counter.v stein_l2trig.v \
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stein_adc_controller.v leadingbit.v stein_ix_acquire_switch.v countbits.v stein_channel_map.v \
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barrel.v priority_encoder.v adc128s102.v idefx.v \
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serializer.v \
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ix.v testpulser.v
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stein_FLAGS = -sstein_test -DSTEIN_TEST -DUART3MHZ -DINFERRED_SRAM -DM24MHZ -DTRIG_NOINVERT
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step.vvp: step.v stein_core.v stein_pha.v frontend.v backend.v memport.v por.v \
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message.v uart.v l3code.v crc.v msg_regs.v \
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mem.v fifo.v hamming.v counters.v \
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ppsschedule.v pha.v eeprom.v l3registerfile.v \
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processor.v l3regfifo.v adder.v adderi.v mult.v log7to4.v trim.v bitrange.v cmp.v \
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compression.v encode.v itof.v log2by8.v \
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opheater.v sfilter.v \
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stein_channel_map.v \
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stein_middleend.v stein_frontend.v clk_domain_switch.v stein_ix_controller.v stein_l1_counter.v stein_l2trig.v \
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stein_adc_controller.v leadingbit.v stein_ix_acquire_switch.v countbits.v \
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barrel.v priority_encoder.v adc128s102.v idefx.v \
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serializer.v \
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ix.v testpulser.v actel.v
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step_FLAGS = -sstep_test -DSTEP_TEST -DUART3MHZ -DINFERRED_SRAM -DM24MHZ -DTRIG_NOINVERT -DARxSTREAM
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l3win_test.vvp: step_l3win_test.v stein_pha.v backend.v hamming.v \
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l3code.v l3registerfile.v ppsschedule.v memport.v fifo.v \
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message.v pha.v eeprom.v msg_regs.v counters.v mem.v \
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compression.v encode.v itof.v log2by8.v \
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processor.v l3regfifo.v log7to4.v adder.v trim.v cmp.v adderi.v mult.v bitrange.v \
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step.l3v step_dps.iv stein_channel_map.v countbits.v
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l3win_test_FLAGS = -sl3win_test -DL3WIN_TEST -DUART3MHZ -DINFERRED_SRAM -DM24MHZ -DTRIG_NOINVERT -DARxSTREAM
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QUARTUS=/usr/local/quartus/altera9.1sp1/quartus
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export PATH:=$(PATH):$(QUARTUS)/bin
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MAPFLGS = $(patsubst %, --verilog_macro="%",$($*_MAPDEFS))
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%.rbf: %.qpf %.qsf %.sdc %.v
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quartus_map $< $(MAPFLGS)
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quartus_fit $<
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quartus_asm $<
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quartus_sta $<
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grep -i warning $*.*.rpt \
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| grep -v 'truncated value with size 32 to match size of target' \
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| grep -v 'behaves as a Local Parameter Declaration because the module has a Module Parameter Port List' \
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> $*.warnings
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stein.rbf: pll96.v stein.v stein_core.v stein_pha.v stein_channel_map.v \
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stein_frontend.v stein_middleend.v \
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stein_ix_controller.v clk_domain_switch.v stein_l1_counter.v stein_l2trig.v \
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stein_adc_controller.v leadingbit.v countbits.v stein_ix_acquire_switch.v \
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barrel.v priority_encoder.v adc128s102.v \
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memport.v backend.v message.v uart.v por.v ix.v testpulser.v \
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l3code.v crc.v msg_regs.v fifo.v hamming.v mem.v \
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counters.v ppsschedule.v pha.v eeprom.v l3registerfile.v \
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l3/processor.v l3/l3regfifo.v l3/adder.v l3/adderi.v l3/mult.v \
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l3/log7to4.v l3/trim.v l3/bitrange.v l3/cmp.v \
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encode/compression.v encode/encode.v itof.v log2by8.v opheater.v sfilter.v \
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stein_test.rbf: pll96.v stein.v stein_core.v stein_pha.v \
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stein_frontend.v stein_middleend.v \
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memport.v backend.v message.v uart.v \
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l3code.v crc.v msg_regs.v fifo.v hamming.v mem.v \
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counters.v ppsschedule.v pha.v eeprom.v l3registerfile.v \
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l3/processor.v l3/l3regfifo.v l3/adder.v l3/adderi.v l3/mult.v \
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l3/log7to4.v l3/trim.v l3/bitrange.v l3/cmp.v \
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encode/compression.v encode/encode.v itof.v sfilter.v \
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clk_domain_switch.v stein_ix_controller.v stein_l1_counter.v stein_l2trig.v \
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stein_adc_controller.v leadingbit.v stein_ix_acquire_switch.v countbits.v \
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barrel.v priority_encoder.v
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rm -f stein.rbf
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$(MAKE) stein_MAPDEFS=TRIG_NOINVERT=1 stein.rbf
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mv stein.rbf $@
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mv stein.warnings stein_test.warnings
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stein_ix_controller_acquire.vvp: stein_ix_controller.v stein_adc_controller.v stein_l2trig.v countbits.v memWxActel.v RAM64K36_sim.v mem36x128.v mem.v hamming.v sfilter.v barrel.v priority_encoder.v adc128s102.v idefx.v ix.v stein_channel_map.v
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stein_ix_controller_acquire_FLAGS = -DIX_ACQUIRE_TEST -DTARGET_ACTEL -six_acquire_test -DARxSTREAM
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stein_adc_controller.vvp: stein_adc_controller.v barrel.v priority_encoder.v adc128s102.v
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stein_adc_controller_FLAGS = -DSTEIN_ADC_CONTROLLER_TEST -sstein_adc_controller_test
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stein_ix_controller_temp.vvp: stein_ix_controller.v stein_adc_controller.v sfilter.v barrel.v priority_encoder.v adc128s102.v
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stein_ix_controller_temp_FLAGS = -DIX_TEMP_TEST -six_temp_test
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stein_ix_controller_sc.vvp: stein_ix_controller.v leadingbit.v idefx.v ix.v
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stein_ix_controller_sc_FLAGS = -DIX_SC_SCHEDULER_TEST -six_sc_scheduler_test
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stein_hk.vvp: stein_core.v stein_pha.v stein_ix_controller.v stein_adc_controller.v sfilter.v barrel.v priority_encoder.v countbits.v adc128s102.v
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stein_hk_FLAGS = -DSTEIN_HK_TEST -sstein_hk_test
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stein_ix_controller_reset.vvp: stein_ix_controller.v
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stein_ix_controller_reset_FLAGS = -DIX_RESET_TEST -six_reset_test
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stein_ix_acquire_switch.vvp: stein_ix_acquire_switch.v stein_ix_controller.v stein_adc_controller.v stein_l2trig.v countbits.v memWxActel.v RAM64K36_sim.v mem36x128.v mem.v hamming.v sfilter.v barrel.v priority_encoder.v clk_domain_switch.v adc128s102.v
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stein_ix_acquire_switch_FLAGS = -DIX_ACQUIRE_SWITCH_TEST -DINFERRED_SRAM -DM24MHZ -six_acquire_switch_test
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clk_domain_switch.vvp: clk_domain_switch.v
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clk_domain_switch_FLAGS = -DCLK_DOMAIN_SWITCH_TEST -DM24MHZ -sclk_domain_switch_test
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stein_frontend.vvp: stein_frontend.v stein_adc_controller.v stein_ix_controller.v adc128s102.v barrel.v priority_encoder.v stein_l1_counter.v stein_l2trig.v counters.v countbits.v leadingbit.v idefx.v
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stein_frontend_FLAGS = -DSTEIN_FRONTEND_TEST -sstein_frontend_test
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idefx.vvp: idefx.v
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idefx_FLAGS = -DIDEFX_TEST -sidefx_test
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stein_l2trig.vvp: stein_l2trig.v countbits.v
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stein_l2trig_FLAGS = -DSTEIN_L2TRIG_TEST -sstein_l2trig_test
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stein_middleend.vvp: stein_middleend.v stein_ix_controller.v stein_l1_counter.v countbits.v leadingbit.v idefx.v counters.v
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stein_middleend_FLAGS = -DSTEIN_MIDDLEEND_TEST -sstein_middleend_test
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stein_sc_write.vvp: stein_core.v stein_pha.v
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stein_sc_write_FLAGS = -DSC_WRITE_TEST -ssc_write_test
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stein_package_maker.vvp: stein_pha.v stein_ix_acquire_switch.v stein_ix_controller.v stein_adc_controller.v stein_l2trig.v countbits.v memWxActel.v RAM64K36_sim.v mem36x128.v mem.v hamming.v sfilter.v barrel.v priority_encoder.v clk_domain_switch.v adc128s102.v
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stein_package_maker_FLAGS = -DSTEIN_PACKAGE_MAKER_TEST -DINFERRED_SRAM -DM24MHZ -sstein_package_maker_test
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i14tof11.vvp: stein_core.v
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i14tof11_FLAGS = -DI14TOF11_TEST -si14tof11_test
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%.l3v: %.l3
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$(MAKE) -C ../../sirena/altera ../../stein/altera/$@
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