thhor_crs/fpga/thhor_crs.sdc

create_clock -name xclk    -period 31.25 xclk
create_clock -name spi_sck -period 200   spi_sck
create_clock -name ARxC    -period 10    S_IN
derive_clock_uncertainty
set_false_path -from spi_sck -to xclk
set_false_path -from xclk -to  spi_sck
set_false_path -from ARxC -to xclk
set_false_path -from xclk -to ARxC
stis_slice, nm_counters, pressure, ax_port 2026-03-16 08:22:49 +01:00			`create_clock -name xclk -period 31.25 xclk`
			`create_clock -name spi_sck -period 200 spi_sck`
			`create_clock -name ARxC -period 10 S_IN`
fpga: nmrena unmodified 2025-12-21 21:40:54 +01:00			`derive_clock_uncertainty`
fpga pinout, with fixes on the schematics and layout 2025-12-21 23:27:15 +01:00			`set_false_path -from spi_sck -to xclk`
			`set_false_path -from xclk -to spi_sck`
stis_slice, nm_counters, pressure, ax_port 2026-03-16 08:22:49 +01:00			`set_false_path -from ARxC -to xclk`
			`set_false_path -from xclk -to ARxC`