Stephan I. Böttcher
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3f9a100e7c
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fpga spi_slave: longer sclk timeout
The µC needs about 5 µs between bytes. The 128 mclk timeout @32MHz is
4.3µs. This commit extends the timeout to 1024 mclk cycles.
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2026-03-25 20:20:07 +01:00 |
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Stephan I. Böttcher
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3866de5c07
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fpga/Makefile: iverilog v14
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2026-03-18 20:55:59 +01:00 |
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Stephan I. Böttcher
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1a41e4ceca
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move net delc before use
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2026-03-16 22:26:27 +01:00 |
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Stephan
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31827d094c
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stis_slice, nm_counters, pressure, ax_port
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2026-03-16 08:22:49 +01:00 |
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Stephan I. Böttcher
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9c9d89f454
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altera synthesis of empty design succeeds
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2025-12-22 00:02:43 +01:00 |
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Stephan I. Böttcher
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a908ac1c8f
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fpga pinout, with fixes on the schematics and layout
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2025-12-21 23:27:15 +01:00 |
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Stephan I. Böttcher
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00c0cddffe
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fpga: nmrena unmodified
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2025-12-21 21:40:54 +01:00 |
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