4 commits

Author	SHA1	Message	Date
Stephan I. Böttcher	3866de5c07	fpga/Makefile: iverilog v14	2026-03-18 20:55:59 +01:00
Stephan I. Böttcher	1a41e4ceca	move net delc before use	2026-03-16 22:26:27 +01:00
Stephan	31827d094c	stis_slice, nm_counters, pressure, ax_port	2026-03-16 08:22:49 +01:00
Stephan I. Böttcher	9c9d89f454	altera synthesis of empty design succeeds	2025-12-22 00:02:43 +01:00