Stephan/thhor_crs
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301 commits 3 branches 0 tags 6.7 MiB
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3 commits

Author SHA1 Message Date
Stephan I. Böttcher
3f9a100e7c fpga spi_slave: longer sclk timeout 
The µC needs about 5 µs between bytes.  The 128 mclk timeout @32MHz is
4.3µs.  This commit extends the timeout to 1024 mclk cycles.
 2026-03-25 20:20:07 +01:00
Stephan
31827d094c stis_slice, nm_counters, pressure, ax_port 2026-03-16 08:22:49 +01:00
Stephan I. Böttcher
9c9d89f454 altera synthesis of empty design succeeds 2025-12-22 00:02:43 +01:00